Home
last modified time | relevance | path

Searched refs:WMSK_BIT (Results 1 – 14 of 14) sorted by relevance

/rk3399_ARM-atf/plat/rockchip/rk3288/drivers/secure/
H A Dsecure.h38 #define SGRF_FAST_BOOT_DIS WMSK_BIT(8)
40 #define SGRF_PCLK_WDT_UNGATE WMSK_BIT(6)
56 #define SGRF_SLV_SEC_NO_BYPS WMSK_BIT(15)
67 #define SGRF_DDR_RGN_NO_BYPS WMSK_BIT(15)
71 #define SGRF_DAPDEVICE_MSK WMSK_BIT(0)
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/pmu/
H A Dm0_ctl.c23 mmio_write_32(SGRF_BASE + SGRF_PMU_CON(0), WMSK_BIT(7)); in m0_init()
24 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), WMSK_BIT(12)); in m0_init()
40 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, WMSK_BIT(5)); in m0_init()
H A Dpmu.h65 #define CCI_FORCE_WAKEUP WMSK_BIT(8)
66 #define EXTERNAL_32K WMSK_BIT(0)
H A Dpmu.c844 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3), WMSK_BIT(1)); in sys_slp_config()
1464 WMSK_BIT(PMU_CLR_PREQ_CCI500_HW) | in rockchip_soc_sys_pwr_dm_resume()
1465 WMSK_BIT(PMU_CLR_QREQ_CCI500_HW) | in rockchip_soc_sys_pwr_dm_resume()
1466 WMSK_BIT(PMU_QGATING_CCI500_CFG)); in rockchip_soc_sys_pwr_dm_resume()
1472 WMSK_BIT(PMU_PWRDWN_REQ_CORE_B_2GIC_SW) | in rockchip_soc_sys_pwr_dm_resume()
1473 WMSK_BIT(PMU_PWRDWN_REQ_CORE_B_SW) | in rockchip_soc_sys_pwr_dm_resume()
1474 WMSK_BIT(PMU_PWRDWN_REQ_GIC2_CORE_B_SW) | in rockchip_soc_sys_pwr_dm_resume()
1475 WMSK_BIT(PMU_CLR_CORE_L_HW) | in rockchip_soc_sys_pwr_dm_resume()
1476 WMSK_BIT(PMU_CLR_CORE_L_2GIC_HW) | in rockchip_soc_sys_pwr_dm_resume()
1477 WMSK_BIT(PMU_CLR_GIC2_CORE_L_HW)); in rockchip_soc_sys_pwr_dm_resume()
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/secure/
H A Dsecure.h36 #define SGRF_PMU_SLV_S_CFGED WMSK_BIT(0)
37 #define SGRF_PMU_SLV_CRYPTO1_NS WMSK_BIT(1)
52 #define SGRF_DDR_RGN_NO_BYPS WMSK_BIT(9)
H A Dsecure.c105 WMSK_BIT(PCLK_WDT_CA53_GATE_SHIFT) | in secure_watchdog_ungate()
106 WMSK_BIT(PCLK_WDT_CM0_GATE_SHIFT)); in secure_watchdog_ungate()
/rk3399_ARM-atf/plat/rockchip/rk3568/drivers/scmi/
H A Drk3568_clk.c39 #define CLK_CORE_I_SEL_APLL WMSK_BIT(6)
45 #define CLK_CORE_SEL_CORE_I WMSK_BIT(7)
49 #define CLK_CORE_NDFT_CLK_CORE WMSK_BIT(15)
67 #define SCLK_PATH_NOR_APLL (BITS_WITH_WMASK(0, 0x3, 8) | WMSK_BIT(15))
68 #define SCLK_PATH_NOR_GPLL (BITS_WITH_WMASK(0x1, 0x3, 8) | WMSK_BIT(15))
69 #define SCLK_PATH_NOR_NPLL BITS_WITH_WMASK(0x2, 0x3, 8) | WMSK_BIT(15)
73 #define CLK_NPU_SRC_NPLL WMSK_BIT(6)
76 #define CLK_NPU_NP5_SRC_NPLL WMSK_BIT(7)
79 #define NPU_PRE_CLK_SEL_PLL_SRC WMSK_BIT(8)
82 #define CLK_NPU_MUX_PLL_SRC WMSK_BIT(15)
[all …]
/rk3399_ARM-atf/plat/rockchip/common/include/
H A Dplat_private.h45 #ifndef WMSK_BIT
46 #define WMSK_BIT(nr) BIT((nr) + REG_MSK_SHIFT) macro
51 #define BIT_WITH_WMSK(nr) (BIT(nr) | WMSK_BIT(nr))
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/soc/
H A Dsoc.h42 #define PLL_NO_BYPASS_MODE WMSK_BIT(PLL_BYPASS_SHIFT)
182 #define CRU_DMAC0_RST_RLS WMSK_BIT(3)
186 #define CRU_DMAC1_RST_RLS WMSK_BIT(4)
204 #define CRU_PMU_SGRF_RST_RLS WMSK_BIT(6)
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/scmi/
H A Drk3588_clk.c72 #define CRU_PLL_POWER_UP WMSK_BIT(13)
75 #define CLK_CORE_I_SEL_APLL WMSK_BIT(6)
126 #define SCLK_DSU_PATH_NOR_PLL WMSK_BIT(0)
136 #define NPU_CLK_PATH_NOR_PLL WMSK_BIT(0)
145 #define GPU_CLK_PATH_NOR_PLL WMSK_BIT(14)
1130 WMSK_BIT(11)); in clk_scmi_sbus_set_rate()
1138 BIT_WITH_WMSK(11) | WMSK_BIT(10)); in clk_scmi_sbus_set_rate()
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/
H A Dsuspend.c45 #define PRESET_GPIO0_HOLD(n) (((n) << 7) | WMSK_BIT(7))
46 #define PRESET_GPIO1_HOLD(n) (((n) << 8) | WMSK_BIT(8))
/rk3399_ARM-atf/plat/rockchip/rk3576/scmi/
H A Drk3576_clk.c72 #define CRU_PLL_POWER_UP WMSK_BIT(13)
121 #define NPU_CLK_PATH_NOR_PLL WMSK_BIT(15)
132 #define GPU_CLK_PATH_NOR_PLL WMSK_BIT(8)
/rk3399_ARM-atf/plat/rockchip/rk3568/drivers/pmu/
H A Dpmu.c439 WMSK_BIT(core_pm_en + offset)); in cpus_power_domain_on()
/rk3399_ARM-atf/plat/rockchip/rk3328/drivers/pmu/
H A Dpmu.c500 mmio_write_32(DDR_GRF_BASE, BIT_WITH_WMSK(14) | WMSK_BIT(15)); in ddr_suspend()