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Searched refs:TRNG_BASE (Results 1 – 7 of 7) sorted by relevance

/rk3399_ARM-atf/plat/arm/board/juno/
H A Djuno_trng.c36 val = mmio_read_32(TRNG_BASE + TRNG_STATUS); in output_valid()
64 mmio_write_32(TRNG_BASE + TRNG_INTMASK, 0); in plat_get_entropy()
66 mmio_write_32(TRNG_BASE + TRNG_CONFIG, NSAMPLE_CLOCKS); in plat_get_entropy()
68 mmio_write_32(TRNG_BASE + TRNG_CONTROL, 2); in plat_get_entropy()
70 mmio_write_32(TRNG_BASE + TRNG_STATUS, 1); in plat_get_entropy()
77 mmio_write_32(TRNG_BASE + TRNG_CONTROL, 1); in plat_get_entropy()
84 crc_value = __crc32w(crc_value, mmio_read_32(TRNG_BASE + 0)); in plat_get_entropy()
85 crc_value = __crc32w(crc_value, mmio_read_32(TRNG_BASE + 4)); in plat_get_entropy()
88 crc_value = __crc32w(crc_value, mmio_read_32(TRNG_BASE + 8)); in plat_get_entropy()
89 crc_value = __crc32w(crc_value, mmio_read_32(TRNG_BASE + 12)); in plat_get_entropy()
[all …]
H A Djuno_def.h62 #define TRNG_BASE UL(0x7FE60000) macro
/rk3399_ARM-atf/plat/mediatek/drivers/rng/mt8188/
H A Drng_plat.h21 #define RNG_STATUS (TRNG_BASE + 0x0004)
22 #define RNG_SWRST (TRNG_BASE + 0x0010)
23 #define RNG_IRQ_CFG (TRNG_BASE + 0x0014)
24 #define RNG_EN (TRNG_BASE + 0x0020)
25 #define RNG_HTEST (TRNG_BASE + 0x0028)
26 #define RNG_OUT (TRNG_BASE + 0x0030)
27 #define RNG_RAW (TRNG_BASE + 0x0038)
28 #define RNG_SRC (TRNG_BASE + 0x0050)
/rk3399_ARM-atf/plat/mediatek/drivers/rng/mt8186/
H A Drng_plat.h17 #define TRNG_CTRL (TRNG_BASE + 0x0000)
18 #define TRNG_TIME (TRNG_BASE + 0x0004)
19 #define TRNG_DATA (TRNG_BASE + 0x0008)
20 #define TRNG_CONF (TRNG_BASE + 0x000C)
/rk3399_ARM-atf/plat/mediatek/mt8173/include/
H A Dmt8173_def.h28 #define TRNG_BASE (IO_PHYS + 0x20F000) macro
/rk3399_ARM-atf/plat/mediatek/mt8186/include/
H A Dplatform_def.h82 #define TRNG_BASE (IO_PHYS + 0x0020F000) macro
/rk3399_ARM-atf/plat/mediatek/mt8188/include/
H A Dplatform_def.h195 #define TRNG_BASE (IO_PHYS + 0x0020F000) macro