Home
last modified time | relevance | path

Searched refs:SPM_ACK_CHK_CON_3 (Results 1 – 12 of 12) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/
H A Dmt_spm_internal.c604 unsigned int reg = mmio_read_32(SPM_ACK_CHK_CON_3); in __spm_hw_s1_state_monitor()
607 reg = mmio_read_32(SPM_ACK_CHK_CON_3); in __spm_hw_s1_state_monitor()
609 mmio_write_32(SPM_ACK_CHK_CON_3, reg); in __spm_hw_s1_state_monitor()
611 mmio_write_32(SPM_ACK_CHK_CON_3, reg); in __spm_hw_s1_state_monitor()
618 mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_EN, in __spm_hw_s1_state_monitor()
H A Dmt_spm_reg.h452 #define SPM_ACK_CHK_CON_3 (SPM_BASE + 0x948) macro
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/
H A Dmt_spm_internal.c533 reg = mmio_read_32(SPM_ACK_CHK_CON_3); in __spm_hw_s1_state_monitor()
537 mmio_write_32(SPM_ACK_CHK_CON_3, reg); in __spm_hw_s1_state_monitor()
539 mmio_write_32(SPM_ACK_CHK_CON_3, reg); in __spm_hw_s1_state_monitor()
546 mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_EN, in __spm_hw_s1_state_monitor()
H A Dmt_spm_reg.h523 #define SPM_ACK_CHK_CON_3 (SPM_BASE + 0x960) macro
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/
H A Dmt_spm_internal.c571 reg = mmio_read_32(SPM_ACK_CHK_CON_3); in __spm_hw_s1_state_monitor()
575 mmio_write_32(SPM_ACK_CHK_CON_3, reg); in __spm_hw_s1_state_monitor()
577 mmio_write_32(SPM_ACK_CHK_CON_3, reg); in __spm_hw_s1_state_monitor()
584 mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_EN, in __spm_hw_s1_state_monitor()
H A Dmt_spm_reg.h507 #define SPM_ACK_CHK_CON_3 (SPM_BASE + 0x960) macro
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8188/
H A Dmt_spm_internal.c451 mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_CLR_ALL, in __spm_hw_s1_state_monitor()
454 reg = mmio_read_32(SPM_ACK_CHK_CON_3); in __spm_hw_s1_state_monitor()
462 mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_EN, in __spm_hw_s1_state_monitor()
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/
H A Dmt_spm_internal.c817 reg = mmio_read_32(SPM_ACK_CHK_CON_3); in __spm_hw_s1_state_monitor()
819 mmio_write_32(SPM_ACK_CHK_CON_3, reg); in __spm_hw_s1_state_monitor()
821 mmio_write_32(SPM_ACK_CHK_CON_3, reg); in __spm_hw_s1_state_monitor()
823 reg = mmio_read_32(SPM_ACK_CHK_CON_3); in __spm_hw_s1_state_monitor()
833 mmio_write_32(SPM_ACK_CHK_CON_3, reg); in __spm_hw_s1_state_monitor()
H A Dmt_spm_reg.h433 #define SPM_ACK_CHK_CON_3 (SPM_BASE + 0x9F8) macro
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/
H A Dmt_spm_internal.c810 mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, in __spm_hw_s1_state_monitor()
815 reg = mmio_read_32(SPM_ACK_CHK_CON_3); in __spm_hw_s1_state_monitor()
821 mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_EN, in __spm_hw_s1_state_monitor()
H A Dmt_spm_reg.h707 #define SPM_ACK_CHK_CON_3 (SPM_BASE + 0x9614) macro
/rk3399_ARM-atf/plat/mediatek/mt8188/include/
H A Dspm_reg.h453 #define SPM_ACK_CHK_CON_3 (SPM_BASE + 0x960) macro