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Searched refs:REG (Results 1 – 6 of 6) sorted by relevance

/rk3399_ARM-atf/drivers/arm/gic/v3/
H A Dgicv3_private.h29 #define BIT_NUM(REG, id) \ argument
30 ((id) & ((1U << REG##R_SHIFT) - 1U))
38 #define GICD_OFFSET_8(REG, id) \ argument
40 GICD_##REG##R + (uintptr_t)(id) : \
41 GICD_##REG##RE + (uintptr_t)(id) - MIN_ESPI_ID)
43 #define GICD_OFFSET(REG, id) \ argument
45 GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2) : \
46 GICD_##REG##RE + ((((uintptr_t)(id) - MIN_ESPI_ID) >> \
47 REG##R_SHIFT) << 2))
49 #define GICD_OFFSET_64(REG, id) \ argument
[all …]
H A Dgicv3_main.c51 #define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \ argument
54 int_id += (1U << REG##R_SHIFT)) { \
57 REG##R_SHIFT]); \
61 #define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \ argument
64 int_id += (1U << REG##R_SHIFT)) { \
66 REG##R_SHIFT] = gicd_read_##reg((base), int_id); \
71 #define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) \ argument
74 int_id += (1U << REG##R_SHIFT)) { \
77 round_up(TOTAL_SPI_INTR_NUM, 1U << REG##R_SHIFT)))\
78 >> REG##R_SHIFT]); \
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/apusys/
H A Dapupwr_clkctl_def.h71 #define apupwr_writel(VAL, REG) mmio_write_32((uintptr_t)REG, VAL) argument
72 #define apupwr_writel_relax(VAL, REG) mmio_write_32_relax((uintptr_t)REG, VAL) argument
73 #define apupwr_readl(REG) mmio_read_32((uintptr_t)REG) argument
74 #define apupwr_clrbits(VAL, REG) mmio_clrbits_32((uintptr_t)REG, VAL) argument
75 #define apupwr_setbits(VAL, REG) mmio_setbits_32((uintptr_t)REG, VAL) argument
76 #define apupwr_clrsetbits(CLR_VAL, SET_VAL, REG) \ argument
77 mmio_clrsetbits_32((uintptr_t)REG, CLR_VAL, SET_VAL)
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/apusys/
H A Dmtk_apusys_apc_def.h85 #define apuapc_writel(VAL, REG) mmio_write_32((uintptr_t)REG, VAL) argument
86 #define apuapc_readl(REG) mmio_read_32((uintptr_t)REG) argument
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/devapc/
H A Ddevapc.h173 #define devapc_writel(VAL, REG) mmio_write_32((uintptr_t)REG, VAL) argument
174 #define devapc_readl(REG) mmio_read_32((uintptr_t)REG) argument
/rk3399_ARM-atf/docs/plat/marvell/armada/misc/
H A Dmvebu-io-win.rst44 {0x00000000ffe00000, 0x000000000100000, PCIE_REGS_TID}, /* PCI-REG window 64Kb for PCIe-reg*/