1*296b5902SFlora Fu /* 2*296b5902SFlora Fu * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 3*296b5902SFlora Fu * 4*296b5902SFlora Fu * SPDX-License-Identifier: BSD-3-Clause 5*296b5902SFlora Fu */ 6*296b5902SFlora Fu 7*296b5902SFlora Fu #ifndef APUPWR_CLKCTL_DEF_H 8*296b5902SFlora Fu #define APUPWR_CLKCTL_DEF_H 9*296b5902SFlora Fu 10*296b5902SFlora Fu #include <lib/mmio.h> 11*296b5902SFlora Fu 12*296b5902SFlora Fu enum dvfs_voltage_domain { 13*296b5902SFlora Fu V_VPU0 = 0, 14*296b5902SFlora Fu V_VPU1 = 1, 15*296b5902SFlora Fu V_MDLA0 = 2, 16*296b5902SFlora Fu V_MDLA1 = 3, 17*296b5902SFlora Fu V_APU_CONN = 4, 18*296b5902SFlora Fu V_TOP_IOMMU = 5, 19*296b5902SFlora Fu V_VCORE = 6, 20*296b5902SFlora Fu APUSYS_BUCK_DOMAIN_NUM = 7, 21*296b5902SFlora Fu }; 22*296b5902SFlora Fu 23*296b5902SFlora Fu enum dvfs_freq { 24*296b5902SFlora Fu DVFS_FREQ_NOT_SUPPORT = 0, 25*296b5902SFlora Fu DVFS_FREQ_ACC_26M = 1, 26*296b5902SFlora Fu DVFS_FREQ_ACC_PARKING = 2, 27*296b5902SFlora Fu DVFS_FREQ_ACC_SOC = 3, 28*296b5902SFlora Fu DVFS_FREQ_ACC_APUPLL = 4, 29*296b5902SFlora Fu DVFS_FREQ_00_026000_F = 26000, 30*296b5902SFlora Fu DVFS_FREQ_00_208000_F = 208000, 31*296b5902SFlora Fu DVFS_FREQ_00_238000_F = 238000, 32*296b5902SFlora Fu DVFS_FREQ_00_273000_F = 273000, 33*296b5902SFlora Fu DVFS_FREQ_00_312000_F = 312000, 34*296b5902SFlora Fu DVFS_FREQ_00_358000_F = 358000, 35*296b5902SFlora Fu DVFS_FREQ_00_385000_F = 385000, 36*296b5902SFlora Fu DVFS_FREQ_00_499200_F = 499200, 37*296b5902SFlora Fu DVFS_FREQ_00_500000_F = 500000, 38*296b5902SFlora Fu DVFS_FREQ_00_525000_F = 525000, 39*296b5902SFlora Fu DVFS_FREQ_00_546000_F = 546000, 40*296b5902SFlora Fu DVFS_FREQ_00_594000_F = 594000, 41*296b5902SFlora Fu DVFS_FREQ_00_624000_F = 624000, 42*296b5902SFlora Fu DVFS_FREQ_00_688000_F = 688000, 43*296b5902SFlora Fu DVFS_FREQ_00_687500_F = 687500, 44*296b5902SFlora Fu DVFS_FREQ_00_728000_F = 728000, 45*296b5902SFlora Fu DVFS_FREQ_00_800000_F = 800000, 46*296b5902SFlora Fu DVFS_FREQ_00_832000_F = 832000, 47*296b5902SFlora Fu DVFS_FREQ_00_960000_F = 960000, 48*296b5902SFlora Fu DVFS_FREQ_00_1100000_F = 1100000, 49*296b5902SFlora Fu }; 50*296b5902SFlora Fu #define DVFS_FREQ_MAX (DVFS_FREQ_00_1100000_F) 51*296b5902SFlora Fu 52*296b5902SFlora Fu enum pll_set_rate_mode { 53*296b5902SFlora Fu CON0_PCW = 0, 54*296b5902SFlora Fu FHCTL_SW = 1, 55*296b5902SFlora Fu FHCTL_HW = 2, 56*296b5902SFlora Fu PLL_SET_RATE_MODE_MAX = 3, 57*296b5902SFlora Fu }; 58*296b5902SFlora Fu 59*296b5902SFlora Fu enum apupll { 60*296b5902SFlora Fu APUPLL = 0, 61*296b5902SFlora Fu NPUPLL = 1, 62*296b5902SFlora Fu APUPLL1 = 2, 63*296b5902SFlora Fu APUPLL2 = 3, 64*296b5902SFlora Fu APUPLL_MAX = 4, 65*296b5902SFlora Fu }; 66*296b5902SFlora Fu 67*296b5902SFlora Fu #define BUCK_VVPU_DOMAIN_DEFAULT_FREQ (DVFS_FREQ_00_273000_F) 68*296b5902SFlora Fu #define BUCK_VMDLA_DOMAIN_DEFAULT_FREQ (DVFS_FREQ_00_312000_F) 69*296b5902SFlora Fu #define BUCK_VCONN_DOMAIN_DEFAULT_FREQ (DVFS_FREQ_00_208000_F) 70*296b5902SFlora Fu 71*296b5902SFlora Fu #define apupwr_writel(VAL, REG) mmio_write_32((uintptr_t)REG, VAL) 72*296b5902SFlora Fu #define apupwr_writel_relax(VAL, REG) mmio_write_32_relax((uintptr_t)REG, VAL) 73*296b5902SFlora Fu #define apupwr_readl(REG) mmio_read_32((uintptr_t)REG) 74*296b5902SFlora Fu #define apupwr_clrbits(VAL, REG) mmio_clrbits_32((uintptr_t)REG, VAL) 75*296b5902SFlora Fu #define apupwr_setbits(VAL, REG) mmio_setbits_32((uintptr_t)REG, VAL) 76*296b5902SFlora Fu #define apupwr_clrsetbits(CLR_VAL, SET_VAL, REG) \ 77*296b5902SFlora Fu mmio_clrsetbits_32((uintptr_t)REG, CLR_VAL, SET_VAL) 78*296b5902SFlora Fu 79*296b5902SFlora Fu /* PLL and related register */ 80*296b5902SFlora Fu #define APU_PLL_BASE (APUSYS_APU_PLL_BASE) 81*296b5902SFlora Fu #define APU_PLL4H_PLL1_CON0 (APU_PLL_BASE + 0x008) 82*296b5902SFlora Fu #define APU_PLL4H_PLL1_CON1 (APU_PLL_BASE + 0x00C) 83*296b5902SFlora Fu #define APU_PLL4H_PLL1_CON3 (APU_PLL_BASE + 0x014) 84*296b5902SFlora Fu 85*296b5902SFlora Fu #define APU_PLL4H_PLL2_CON0 (APU_PLL_BASE + 0x018) 86*296b5902SFlora Fu #define APU_PLL4H_PLL2_CON1 (APU_PLL_BASE + 0x01C) 87*296b5902SFlora Fu #define APU_PLL4H_PLL2_CON3 (APU_PLL_BASE + 0x024) 88*296b5902SFlora Fu 89*296b5902SFlora Fu #define APU_PLL4H_PLL3_CON0 (APU_PLL_BASE + 0x028) 90*296b5902SFlora Fu #define APU_PLL4H_PLL3_CON1 (APU_PLL_BASE + 0x02C) 91*296b5902SFlora Fu #define APU_PLL4H_PLL3_CON3 (APU_PLL_BASE + 0x034) 92*296b5902SFlora Fu 93*296b5902SFlora Fu #define APU_PLL4H_PLL4_CON0 (APU_PLL_BASE + 0x038) 94*296b5902SFlora Fu #define APU_PLL4H_PLL4_CON1 (APU_PLL_BASE + 0x03C) 95*296b5902SFlora Fu #define APU_PLL4H_PLL4_CON3 (APU_PLL_BASE + 0x044) 96*296b5902SFlora Fu 97*296b5902SFlora Fu #define APU_PLL4H_FHCTL_HP_EN (APU_PLL_BASE + 0x0E00) 98*296b5902SFlora Fu #define APU_PLL4H_FHCTL_UNITSLOPE_EN (APU_PLL_BASE + 0x0E04) 99*296b5902SFlora Fu #define APU_PLL4H_FHCTL_CLK_CON (APU_PLL_BASE + 0x0E08) 100*296b5902SFlora Fu #define APU_PLL4H_FHCTL_RST_CON (APU_PLL_BASE + 0x0E0C) 101*296b5902SFlora Fu #define APU_PLL4H_FHCTL_SLOPE0 (APU_PLL_BASE + 0x0E10) 102*296b5902SFlora Fu #define APU_PLL4H_FHCTL_SLOPE1 (APU_PLL_BASE + 0x0E14) 103*296b5902SFlora Fu #define APU_PLL4H_FHCTL_DSSC_CFG (APU_PLL_BASE + 0x0E18) 104*296b5902SFlora Fu #define APU_PLL4H_FHCTL_DSSC0_CON (APU_PLL_BASE + 0x0E1C) 105*296b5902SFlora Fu #define APU_PLL4H_FHCTL_DSSC1_CON (APU_PLL_BASE + 0x0E20) 106*296b5902SFlora Fu #define APU_PLL4H_FHCTL_DSSC2_CON (APU_PLL_BASE + 0x0E24) 107*296b5902SFlora Fu #define APU_PLL4H_FHCTL_DSSC3_CON (APU_PLL_BASE + 0x0E28) 108*296b5902SFlora Fu #define APU_PLL4H_FHCTL_DSSC4_CON (APU_PLL_BASE + 0x0E2C) 109*296b5902SFlora Fu #define APU_PLL4H_FHCTL_DSSC5_CON (APU_PLL_BASE + 0x0E30) 110*296b5902SFlora Fu #define APU_PLL4H_FHCTL_DSSC6_CON (APU_PLL_BASE + 0x0E34) 111*296b5902SFlora Fu #define APU_PLL4H_FHCTL_DSSC7_CON (APU_PLL_BASE + 0x0E38) 112*296b5902SFlora Fu #define APU_PLL4H_FHCTL0_CFG (APU_PLL_BASE + 0x0E3C) 113*296b5902SFlora Fu #define APU_PLL4H_FHCTL0_UPDNLMT (APU_PLL_BASE + 0x0E40) 114*296b5902SFlora Fu #define APU_PLL4H_FHCTL0_DDS (APU_PLL_BASE + 0x0E44) 115*296b5902SFlora Fu #define APU_PLL4H_FHCTL0_DVFS (APU_PLL_BASE + 0x0E48) 116*296b5902SFlora Fu #define APU_PLL4H_FHCTL0_MON (APU_PLL_BASE + 0x0E4C) 117*296b5902SFlora Fu #define APU_PLL4H_FHCTL1_CFG (APU_PLL_BASE + 0x0E50) 118*296b5902SFlora Fu #define APU_PLL4H_FHCTL1_UPDNLMT (APU_PLL_BASE + 0x0E54) 119*296b5902SFlora Fu #define APU_PLL4H_FHCTL1_DDS (APU_PLL_BASE + 0x0E58) 120*296b5902SFlora Fu #define APU_PLL4H_FHCTL1_DVFS (APU_PLL_BASE + 0x0E5C) 121*296b5902SFlora Fu #define APU_PLL4H_FHCTL1_MON (APU_PLL_BASE + 0x0E60) 122*296b5902SFlora Fu #define APU_PLL4H_FHCTL2_CFG (APU_PLL_BASE + 0x0E64) 123*296b5902SFlora Fu #define APU_PLL4H_FHCTL2_UPDNLMT (APU_PLL_BASE + 0x0E68) 124*296b5902SFlora Fu #define APU_PLL4H_FHCTL2_DDS (APU_PLL_BASE + 0x0E6C) 125*296b5902SFlora Fu #define APU_PLL4H_FHCTL2_DVFS (APU_PLL_BASE + 0x0E70) 126*296b5902SFlora Fu #define APU_PLL4H_FHCTL2_MON (APU_PLL_BASE + 0x0E74) 127*296b5902SFlora Fu #define APU_PLL4H_FHCTL3_CFG (APU_PLL_BASE + 0x0E78) 128*296b5902SFlora Fu #define APU_PLL4H_FHCTL3_UPDNLMT (APU_PLL_BASE + 0x0E7C) 129*296b5902SFlora Fu #define APU_PLL4H_FHCTL3_DDS (APU_PLL_BASE + 0x0E80) 130*296b5902SFlora Fu #define APU_PLL4H_FHCTL3_DVFS (APU_PLL_BASE + 0x0E84) 131*296b5902SFlora Fu #define APU_PLL4H_FHCTL3_MON (APU_PLL_BASE + 0x0E88) 132*296b5902SFlora Fu 133*296b5902SFlora Fu /* PLL4H_PLLx_CON0 */ 134*296b5902SFlora Fu #define RG_PLL_EN BIT(0) 135*296b5902SFlora Fu 136*296b5902SFlora Fu /* PLL4H_PLLx_CON1 */ 137*296b5902SFlora Fu #define RG_PLL_SDM_PCW_CHG BIT(31) 138*296b5902SFlora Fu #define POSDIV_SHIFT (24U) 139*296b5902SFlora Fu #define POSDIV_MASK (0x7) 140*296b5902SFlora Fu 141*296b5902SFlora Fu /* PLL4H_PLLx_CON3 */ 142*296b5902SFlora Fu #define DA_PLL_SDM_PWR_ON BIT(0) 143*296b5902SFlora Fu #define DA_PLL_SDM_ISO_EN BIT(1) 144*296b5902SFlora Fu 145*296b5902SFlora Fu /* FHCTLx_DDS */ 146*296b5902SFlora Fu #define DDS_MASK GENMASK_32(21, 0) 147*296b5902SFlora Fu #define PCW_FRACTIONAL_SHIFT 14U 148*296b5902SFlora Fu #define PLL_TGL_ORG BIT(31) 149*296b5902SFlora Fu 150*296b5902SFlora Fu #define PLL_READY_TIME_20US (20U) 151*296b5902SFlora Fu #define PLL_CMD_READY_TIME_1US (1U) 152*296b5902SFlora Fu 153*296b5902SFlora Fu #define FREQ_VCO_MIN (1500U) /* 1500MHz*/ 154*296b5902SFlora Fu #define FREQ_FIN (26U) /* 26M*/ 155*296b5902SFlora Fu 156*296b5902SFlora Fu /* ACC and related register */ 157*296b5902SFlora Fu #define APU_ACC_BASE (APUSYS_APU_ACC_BASE) 158*296b5902SFlora Fu #define APU_ACC_CONFG_SET0 (APU_ACC_BASE + 0x000) 159*296b5902SFlora Fu #define APU_ACC_CONFG_SET1 (APU_ACC_BASE + 0x004) 160*296b5902SFlora Fu #define APU_ACC_CONFG_SET2 (APU_ACC_BASE + 0x008) 161*296b5902SFlora Fu #define APU_ACC_CONFG_SET4 (APU_ACC_BASE + 0x010) 162*296b5902SFlora Fu #define APU_ACC_CONFG_SET5 (APU_ACC_BASE + 0x014) 163*296b5902SFlora Fu #define APU_ACC_CONFG_SET7 (APU_ACC_BASE + 0x01C) 164*296b5902SFlora Fu 165*296b5902SFlora Fu #define APU_ACC_CONFG_CLR0 (APU_ACC_BASE + 0x040) 166*296b5902SFlora Fu #define APU_ACC_CONFG_CLR1 (APU_ACC_BASE + 0x044) 167*296b5902SFlora Fu #define APU_ACC_CONFG_CLR2 (APU_ACC_BASE + 0x048) 168*296b5902SFlora Fu #define APU_ACC_CONFG_CLR4 (APU_ACC_BASE + 0x050) 169*296b5902SFlora Fu #define APU_ACC_CONFG_CLR5 (APU_ACC_BASE + 0x054) 170*296b5902SFlora Fu #define APU_ACC_CONFG_CLR7 (APU_ACC_BASE + 0x05C) 171*296b5902SFlora Fu 172*296b5902SFlora Fu #define APU_ACC_FM_CONFG_SET (APU_ACC_BASE + 0x0C0) 173*296b5902SFlora Fu #define APU_ACC_FM_CONFG_CLR (APU_ACC_BASE + 0x0C4) 174*296b5902SFlora Fu #define APU_ACC_FM_SEL (APU_ACC_BASE + 0x0C8) 175*296b5902SFlora Fu #define APU_ACC_FM_CNT (APU_ACC_BASE + 0x0CC) 176*296b5902SFlora Fu 177*296b5902SFlora Fu /* APU AO control */ 178*296b5902SFlora Fu #define APU_AO_CTRL_BASE (APUSYS_APU_S_S_4_BASE) 179*296b5902SFlora Fu #define APU_CSR_DUMMY_0 (APU_AO_CTRL_BASE + 0x24) 180*296b5902SFlora Fu 181*296b5902SFlora Fu #define AO_MD32_MNOC_MASK (BIT(1) | BIT(0)) 182*296b5902SFlora Fu 183*296b5902SFlora Fu #define BIT_CGEN_F26M (0) 184*296b5902SFlora Fu #define BIT_CGEN_PARK (1) 185*296b5902SFlora Fu #define BIT_CGEN_SOC (2) 186*296b5902SFlora Fu #define BIT_CGEN_APU (3) 187*296b5902SFlora Fu #define BIT_CGEN_OUT (4) 188*296b5902SFlora Fu #define BIT_SEL_PARK (8) 189*296b5902SFlora Fu #define BIT_SEL_F26M (9) 190*296b5902SFlora Fu #define BIT_SEL_APU_DIV2 (10) 191*296b5902SFlora Fu #define BIT_SEL_APU (11) 192*296b5902SFlora Fu #define BIT_SEL_PARK_SRC_OUT (12) 193*296b5902SFlora Fu #define BIT_INVEN_OUT (15) 194*296b5902SFlora Fu 195*296b5902SFlora Fu #endif /* APUPWR_CLKCTL_DEF_H*/ 196