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Searched refs:RD_TO_WR (Results 1 – 6 of 6) sorted by relevance

/rk3399_ARM-atf/plat/intel/soc/stratix10/include/
H A Ds10_memory_controller.h81 #define RD_TO_WR(value) (((value) & 0x00fc0000) >> 18) macro
/rk3399_ARM-atf/plat/intel/soc/agilex5/include/
H A Dagilex5_memory_controller.h82 #define RD_TO_WR(value) (((value) & 0x00fc0000) >> 18) macro
/rk3399_ARM-atf/plat/intel/soc/agilex/include/
H A Dagilex_memory_controller.h82 #define RD_TO_WR(value) (((value) & 0x00fc0000) >> 18) macro
/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_memory_controller.c217 rd_to_wr = RD_TO_WR(data); in configure_ddr_sched_ctrl_regs()
/rk3399_ARM-atf/plat/intel/soc/agilex/soc/
H A Dagilex_memory_controller.c216 rd_to_wr = RD_TO_WR(data); in configure_ddr_sched_ctrl_regs()
/rk3399_ARM-atf/plat/intel/soc/stratix10/soc/
H A Ds10_memory_controller.c245 rd_to_wr = RD_TO_WR(data); in configure_ddr_sched_ctrl_regs()