Home
last modified time | relevance | path

Searched refs:IOHMC_DRAMADDRW_COL_ADDR_WIDTH (Results 1 – 6 of 6) sorted by relevance

/rk3399_ARM-atf/plat/intel/soc/stratix10/include/
H A Ds10_memory_controller.h38 #define IOHMC_DRAMADDRW_COL_ADDR_WIDTH(x) (((x) & 0x0000001f) >> 0) macro
/rk3399_ARM-atf/plat/intel/soc/agilex5/include/
H A Dagilex5_memory_controller.h39 #define IOHMC_DRAMADDRW_COL_ADDR_WIDTH(x) (((x) & 0x0000001f) >> 0) macro
/rk3399_ARM-atf/plat/intel/soc/agilex/include/
H A Dagilex_memory_controller.h39 #define IOHMC_DRAMADDRW_COL_ADDR_WIDTH(x) (((x) & 0x0000001f) >> 0) macro
/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_memory_controller.c190 col = IOHMC_DRAMADDRW_COL_ADDR_WIDTH(data); in configure_ddr_sched_ctrl_regs()
/rk3399_ARM-atf/plat/intel/soc/agilex/soc/
H A Dagilex_memory_controller.c189 col = IOHMC_DRAMADDRW_COL_ADDR_WIDTH(data); in configure_ddr_sched_ctrl_regs()
/rk3399_ARM-atf/plat/intel/soc/stratix10/soc/
H A Ds10_memory_controller.c218 col = IOHMC_DRAMADDRW_COL_ADDR_WIDTH(data); in configure_ddr_sched_ctrl_regs()