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Searched refs:IMX_PCC5_BASE (Results 1 – 6 of 6) sorted by relevance

/rk3399_ARM-atf/plat/imx/imx8ulp/
H A Ddram.c282 mmio_setbits_32(IMX_PCC5_BASE + 0x108, 0x2 << 22); in dram_enter_self_refresh()
284 mmio_setbits_32(IMX_PCC5_BASE + 0x108, (BIT(30) | BIT(28))); in dram_enter_self_refresh()
325 mmio_setbits_32(IMX_PCC5_BASE + 0x108, 0x2 << 22); in dram_enter_retention()
414 mmio_setbits_32(IMX_PCC5_BASE + 0x108, BIT(30)); in dram_exit_retention()
417 mmio_setbits_32(IMX_PCC5_BASE + 0x108, BIT(28)); in dram_exit_retention()
585 mmio_clrbits_32(IMX_PCC5_BASE + 0x108, BIT(30)); in set_ddr_clk()
608 mmio_setbits_32(IMX_PCC5_BASE + 0x108, BIT(30)); in set_ddr_clk()
H A Dimx8ulp_bl31_setup.c65 mmio_write_32(IMX_PCC5_BASE + 0x114, 0xc0000000); in bl31_early_platform_setup2()
H A Dapd_context.c382 val = mmio_read_32(IMX_PCC5_BASE + i * 4); in lpav_ctx_save()
438 mmio_write_32(IMX_PCC5_BASE + i * 4, pcc5_0[i]); in lpav_ctx_restore()
/rk3399_ARM-atf/plat/imx/imx8ulp/scmi/
H A Dscmi_pd.c130 #define PCC_GPU2D (IMX_PCC5_BASE + 0xf0)
131 #define PCC_GPU3D (IMX_PCC5_BASE + 0xf4)
132 #define PCC_EPDC (IMX_PCC5_BASE + 0xcc)
133 #define PCC_CSI (IMX_PCC5_BASE + 0xbc)
134 #define PCC_PXP (IMX_PCC5_BASE + 0xd0)
/rk3399_ARM-atf/plat/imx/imx8ulp/include/
H A Dplatform_def.h74 #define IMX_PCC5_BASE U(0x2da70000) macro
/rk3399_ARM-atf/plat/imx/imx8ulp/xrdc/
H A Dxrdc_core.c310 mmio_write_32(IMX_PCC5_BASE + 0x0, 0xc0000000); in xrdc_apply_lpav_config()