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Searched refs:GPIO4_BASE (Results 1 – 18 of 18) sorted by relevance

/rk3399_ARM-atf/plat/imx/imx93/
H A Dimx93_bl31_setup.c118 mmio_write_32(GPIO4_BASE + 0x10, 0xffffffff); in bl31_plat_arch_setup()
119 mmio_write_32(GPIO4_BASE + 0x14, 0x3); in bl31_plat_arch_setup()
120 mmio_write_32(GPIO4_BASE + 0x18, 0xffffffff); in bl31_plat_arch_setup()
121 mmio_write_32(GPIO4_BASE + 0x1c, 0x3); in bl31_plat_arch_setup()
/rk3399_ARM-atf/plat/imx/imx9/imx95/
H A Dimx95_bl31_setup.c18 GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE
H A Dimx95_psci.c56 GPIO_CTX(GPIO4_BASE, 30U),
/rk3399_ARM-atf/plat/imx/imx9/imx94/
H A Dimx94_bl31_setup.c18 GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE,
H A Dimx94_psci.c62 GPIO_CTX(GPIO4_BASE, 32U),
/rk3399_ARM-atf/plat/imx/imx9/imx95/include/
H A Dplatform_def.h72 #define GPIO4_BASE U(0x43840000) macro
118 #define GPIO4_MAP MAP_REGION_FLAT(GPIO4_BASE, 0x20000, MT_DEVICE | MT_RW)
/rk3399_ARM-atf/plat/imx/imx9/imx94/include/
H A Dplatform_def.h66 #define GPIO4_BASE U(0x43840000) macro
115 #define GPIO4_MAP MAP_REGION_FLAT(GPIO4_BASE, 0x20000, MT_DEVICE | MT_RW)
/rk3399_ARM-atf/plat/hisilicon/hikey/include/
H A Dhi6220.h60 #define GPIO4_BASE 0xF7020000 macro
/rk3399_ARM-atf/plat/rockchip/rk3568/
H A Drk3568_def.h62 #define GPIO4_BASE 0xfe770000 macro
/rk3399_ARM-atf/plat/imx/imx93/include/
H A Dplatform_def.h64 #define GPIO4_BASE U(0x43830000) macro
/rk3399_ARM-atf/plat/rockchip/rk3399/include/shared/
H A Daddressmap_shared.h42 #define GPIO4_BASE (MMIO_BASE + 0x07790000) macro
/rk3399_ARM-atf/plat/rockchip/rk3588/
H A Drk3588_def.h133 #define GPIO4_BASE 0xfec50000 macro
/rk3399_ARM-atf/plat/rockchip/rk3576/
H A Drk3576_def.h131 #define GPIO4_BASE 0x2ae40000 macro
/rk3399_ARM-atf/plat/hisilicon/hikey960/
H A Dhikey960_bl_common.c451 pl061_gpio_register(GPIO4_BASE, 4); in hikey960_gpio_init()
/rk3399_ARM-atf/plat/hisilicon/hikey/
H A Dhikey_bl_common.c57 pl061_gpio_register(GPIO4_BASE, 4); in hikey_gpio_init()
/rk3399_ARM-atf/plat/hisilicon/hikey960/include/
H A Dhi3660.h247 #define GPIO4_BASE UL(0xE8A0F000) macro
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/pmu/
H A Dpmu.c939 gpio_direction[2] = mmio_read_32(GPIO4_BASE + 0x04); in suspend_apio()
1009 mmio_clrbits_32(GPIO4_BASE + 0x04, 0x7fff0000); in suspend_apio()
1026 mmio_clrbits_32(GPIO4_BASE + 0x04, 0x000000ff); in suspend_apio()
1050 mmio_write_32(GPIO4_BASE + 0x04, gpio_direction[2]); in resume_apio()
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/gpio/
H A Drk3399_gpio.c109 .port_base = GPIO4_BASE,