| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | wa_cve_2017_5715_bpiall.S | 26 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
27 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
28 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
29 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
30 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
31 stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
32 stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
33 stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
34 stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
35 stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
[all …]
|
| H A D | wa_cve_2022_23960_bhb.S | 26 str x2, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
38 ldr x2, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
|
| H A D | neoverse_n1.S | 273 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
274 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
275 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
276 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
|
| H A D | wa_cve_2017_5715_mmu.S | 20 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
63 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
|
| H A D | cortex_a76.S | 48 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
50 stp x29, x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
53 ldp x29, x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
70 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
294 ldp x29, x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
|
| H A D | denver.S | 35 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
56 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
|
| /rk3399_ARM-atf/lib/el3_runtime/aarch64/ |
| H A D | context.S | 353 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
354 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
355 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
356 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
357 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
358 stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
359 stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
360 stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
361 stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
362 stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
[all …]
|
| /rk3399_ARM-atf/bl31/aarch64/ |
| H A D | runtime_exceptions.S | 48 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
52 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
89 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
93 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
503 str x0, [x6, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
508 ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
509 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
602 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
603 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
604 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
[all …]
|
| H A D | ea_delegate.S | 120 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
151 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
152 str xzr, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
|
| H A D | crash_reporting.S | 247 add x7, sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0
|
| /rk3399_ARM-atf/include/lib/el3_runtime/aarch64/ |
| H A D | context.h | 37 #define CTX_GPREGS_OFFSET U(0x0) macro
77 #define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END)
366 CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx),
|
| /rk3399_ARM-atf/include/arch/aarch64/ |
| H A D | el3_common_macros.S | 435 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
437 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
|
| /rk3399_ARM-atf/docs/security_advisories/ |
| H A D | security-advisory-tfv-8.rst | 49 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
50 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
|
| /rk3399_ARM-atf/bl1/aarch64/ |
| H A D | bl1_exceptions.S | 85 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
|