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/rk3399_ARM-atf/fdts/
H A Drdaspen-defs.dtsi81 #define CLUSTER_0_DSU_PMU_CPU_LIST <&CPU0>, <&CPU1>
91 #define CLUSTER_0_DSU_PMU_CPU_LIST <&CPU0>, <&CPU1>, <&CPU2>
103 #define CLUSTER_0_DSU_PMU_CPU_LIST <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>
H A Dmorello-fvp.dts64 cpu = <&CPU1>;
84 CPU1: cpu1@100 { label
H A Dtc-base.dtsi79 cpu = <&CPU1>;
137 CPU1:cpu@100 { label
597 cpu = <&CPU1>;
719 affinity = <&CPU0>, <&CPU1>;
757 cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
H A Dfvp-base-gicv5.dtsi34 &CPU1
H A Dfvp-defs.dtsi77 #define CPU_1 CPU(1, c1, p1) /* CPU1: 0.1; 1.0 */
/rk3399_ARM-atf/plat/arm/board/tc/fdts/
H A Dtc_spmc_manifest.dtsi85 CPU1:cpu@100 { label
/rk3399_ARM-atf/plat/marvell/armada/a8k/common/
H A Dplat_pm.c69 CPU1, enumerator
204 if (plat_marvell_cpu_powerdown(CPU1) == -1) in plat_marvell_early_cpu_powerdown()
/rk3399_ARM-atf/docs/design/
H A Dpsci-pd-tree.rst250 CPU1 | 3 | |
H A Dfirmware-design.rst2316 CPU1 updates its per-CPU field of the ``bakery_lock_t`` structure with data cache
2317 disabled. CPU1 then issues a DCIVAC operation to invalidate any stale copies of
2372 | Lock_0 | for CPU1
2375 | Lock_1 | for CPU1
2380 | Lock_N | for CPU1
2389 operation on Lock_N, the corresponding ``bakery_info_t`` in both CPU0 and CPU1
/rk3399_ARM-atf/docs/design_documents/
H A Dpsci_osi_mode.rst490 CPU1: cpu@100 {