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Searched refs:CCPLEX_CSTATE_MASK (Results 1 – 5 of 5) sorted by relevance

/rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/drivers/include/
H A Dmce_private.h20 #define CCPLEX_CSTATE_MASK 0x7U macro
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/drivers/mce/
H A Dnvg.c74 val |= (((uint64_t)ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT) | in nvg_update_cstate_info()
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/drivers/mce/
H A Dnvg.c63 val |= (((uint64_t)ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT) | in nvg_update_cstate_info()
H A Dari.c177 val |= ((ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT) | in ari_update_cstate_info()
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/drivers/include/
H A Dmce_private.h21 #define CCPLEX_CSTATE_MASK ULL(0x3) macro