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Searched refs:CALTIMING3_WR_TO_RD (Results 1 – 6 of 6) sorted by relevance

/rk3399_ARM-atf/plat/intel/soc/stratix10/include/
H A Ds10_memory_controller.h86 #define CALTIMING3_WR_TO_RD(value) (((value) & 0x00000fc0) >> 6) macro
/rk3399_ARM-atf/plat/intel/soc/agilex5/include/
H A Dagilex5_memory_controller.h87 #define CALTIMING3_WR_TO_RD(value) (((value) & 0x00000fc0) >> 6) macro
/rk3399_ARM-atf/plat/intel/soc/agilex/include/
H A Dagilex_memory_controller.h87 #define CALTIMING3_WR_TO_RD(value) (((value) & 0x00000fc0) >> 6) macro
/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_memory_controller.c225 wr_to_rd = CALTIMING3_WR_TO_RD(data); in configure_ddr_sched_ctrl_regs()
/rk3399_ARM-atf/plat/intel/soc/agilex/soc/
H A Dagilex_memory_controller.c224 wr_to_rd = CALTIMING3_WR_TO_RD(data); in configure_ddr_sched_ctrl_regs()
/rk3399_ARM-atf/plat/intel/soc/stratix10/soc/
H A Ds10_memory_controller.c253 wr_to_rd = CALTIMING3_WR_TO_RD(data); in configure_ddr_sched_ctrl_regs()