Searched refs:BIT_WITH_WMSK (Results 1 – 14 of 14) sorted by relevance
37 #define SGRF_FAST_BOOT_ENA BIT_WITH_WMSK(8)39 #define SGRF_PCLK_WDT_GATE BIT_WITH_WMSK(6)41 #define SGRF_PCLK_STIMER_GATE BIT_WITH_WMSK(4)48 #define SGRF_DDRC1_SECURE BIT_WITH_WMSK(12)49 #define SGRF_DDRC0_SECURE BIT_WITH_WMSK(11)50 #define SGRF_PMUSRAM_SECURE BIT_WITH_WMSK(8)51 #define SGRF_WDT_SECURE BIT_WITH_WMSK(7)52 #define SGRF_STIMER_SECURE BIT_WITH_WMSK(6)55 #define SGRF_SLV_SEC_BYPS BIT_WITH_WMSK(15)60 #define SGRF_DDR_RGN_SECURE_SEL BIT_WITH_WMSK(15)[all …]
243 rstnhold_cofig0 = BIT_WITH_WMSK(PRESETN_NOC_PMU_HOLD) | in set_pmu_rsthold()244 BIT_WITH_WMSK(PRESETN_INTMEM_PMU_HOLD) | in set_pmu_rsthold()245 BIT_WITH_WMSK(HRESETN_CM0S_PMU_HOLD) | in set_pmu_rsthold()246 BIT_WITH_WMSK(HRESETN_CM0S_NOC_PMU_HOLD) | in set_pmu_rsthold()247 BIT_WITH_WMSK(DRESETN_CM0S_PMU_HOLD) | in set_pmu_rsthold()248 BIT_WITH_WMSK(POESETN_CM0S_PMU_HOLD) | in set_pmu_rsthold()249 BIT_WITH_WMSK(PRESETN_TIMER_PMU_0_1_HOLD) | in set_pmu_rsthold()250 BIT_WITH_WMSK(RESETN_TIMER_PMU_0_HOLD) | in set_pmu_rsthold()251 BIT_WITH_WMSK(RESETN_TIMER_PMU_1_HOLD) | in set_pmu_rsthold()252 BIT_WITH_WMSK(PRESETN_UART_M0_PMU_HOLD) | in set_pmu_rsthold()[all …]
41 #define PLL_BYPASS_MODE BIT_WITH_WMSK(PLL_BYPASS_SHIFT)180 #define CRU_DMAC0_RST BIT_WITH_WMSK(3)184 #define CRU_DMAC1_RST BIT_WITH_WMSK(4)202 #define CRU_PMU_SGRF_RST_HOLD BIT_WITH_WMSK(6)
34 #define SGRF_PMU_SLV_S_NS BIT_WITH_WMSK(0)46 #define SGRF_DDR_RGN_DPLL_CLK BIT_WITH_WMSK(15) /* DDR PLL output clock */47 #define SGRF_DDR_RGN_RTC_CLK BIT_WITH_WMSK(14) /* 32K clock for DDR PLL */50 #define SGRF_DDR_RGN_BYPS BIT_WITH_WMSK(9)55 #define SGRF_L_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n))57 #define SGRF_H_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n) + 8)
82 BIT_WITH_WMSK(rgn)); in sgrf_ddr_rgn_config()93 BIT_WITH_WMSK(PCLK_WDT_CA53_GATE_SHIFT) | in secure_watchdog_gate()94 BIT_WITH_WMSK(PCLK_WDT_CM0_GATE_SHIFT)); in secure_watchdog_gate()
101 BIT_WITH_WMSK(GRF_SOC_CON2_NSWDT_RST_EN)); in soc_reset_config_all()119 BIT_WITH_WMSK(PMUSGRF_RSTOUT_FST) | in px30_soc_reset_config()120 BIT_WITH_WMSK(PMUSGRF_RSTOUT_TSADC) | in px30_soc_reset_config()121 BIT_WITH_WMSK(PMUSGRF_RSTOUT_WDT)); in px30_soc_reset_config()
40 #define CLK_CORE_I_SEL_GPLL BIT_WITH_WMSK(6)46 #define CLK_CORE_SEL_APLL BIT_WITH_WMSK(7)50 #define CLK_CORE_NDFT_CLK_PVTPLL BIT_WITH_WMSK(15)70 #define SCLK_PATH_DIR_NPLL BIT_WITH_WMSK(15)74 #define CLK_NPU_SRC_GPLL BIT_WITH_WMSK(6)77 #define CLK_NPU_NP5_SRC_GPLL BIT_WITH_WMSK(7)80 #define NPU_PRE_CLK_SEL_NP5 BIT_WITH_WMSK(8)83 #define CLK_NPU_MUX_PVTPLL BIT_WITH_WMSK(15)105 #define GPU_CLK_PATH_PVTPLL BIT_WITH_WMSK(11)
50 #ifndef BIT_WITH_WMSK51 #define BIT_WITH_WMSK(nr) (BIT(nr) | WMSK_BIT(nr)) macro
38 BIT_WITH_WMSK(15) | BITS_WITH_WMASK(0x0, 0x1f, 8)); in m0_init()
851 BIT_WITH_WMSK(PMU_CLR_PREQ_CCI500_HW) | in sys_slp_config()852 BIT_WITH_WMSK(PMU_CLR_QREQ_CCI500_HW) | in sys_slp_config()853 BIT_WITH_WMSK(PMU_QGATING_CCI500_CFG)); in sys_slp_config()856 BIT_WITH_WMSK(PMU_CLR_CORE_L_HW) | in sys_slp_config()857 BIT_WITH_WMSK(PMU_CLR_CORE_L_2GIC_HW) | in sys_slp_config()858 BIT_WITH_WMSK(PMU_CLR_GIC2_CORE_L_HW)); in sys_slp_config()1383 BIT_WITH_WMSK(PMU_PWRDWN_REQ_CORE_B_2GIC_SW) | in rockchip_soc_sys_pwr_dm_suspend()1384 BIT_WITH_WMSK(PMU_PWRDWN_REQ_CORE_B_SW) | in rockchip_soc_sys_pwr_dm_suspend()1385 BIT_WITH_WMSK(PMU_PWRDWN_REQ_GIC2_CORE_B_SW)); in rockchip_soc_sys_pwr_dm_suspend()
71 #define CRU_PLL_POWER_DOWN BIT_WITH_WMSK(13)76 #define CLK_CORE_I_SEL_GPLL BIT_WITH_WMSK(6)127 #define SCLK_DSU_PATH_PVTPLL BIT_WITH_WMSK(0)137 #define NPU_CLK_PATH_PVTPLL BIT_WITH_WMSK(0)146 #define GPU_CLK_PATH_PVTPLL BIT_WITH_WMSK(14)1138 BIT_WITH_WMSK(11) | WMSK_BIT(10)); in clk_scmi_sbus_set_rate()
71 #define CRU_PLL_POWER_DOWN BIT_WITH_WMSK(13)122 #define NPU_CLK_PATH_PVTPLL BIT_WITH_WMSK(15)133 #define GPU_CLK_PATH_PVTPLL BIT_WITH_WMSK(8)
441 BIT_WITH_WMSK(core_pm_sft_wakeup_en + offset)); in cpus_power_domain_on()
500 mmio_write_32(DDR_GRF_BASE, BIT_WITH_WMSK(14) | WMSK_BIT(15)); in ddr_suspend()