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Searched refs:AML_HIU_MAILBOX_CLR_0 (Results 1 – 5 of 5) sorted by relevance

/rk3399_ARM-atf/plat/amlogic/common/
H A Daml_mhu.c42 mmio_write_32(AML_HIU_MAILBOX_CLR_0, 0xFFFFFFFF); in aml_mhu_secure_message_end()
/rk3399_ARM-atf/plat/amlogic/gxbb/
H A Dgxbb_def.h93 #define AML_HIU_MAILBOX_CLR_0 UL(0xDA83C40C) macro
/rk3399_ARM-atf/plat/amlogic/axg/
H A Daxg_def.h99 #define AML_HIU_MAILBOX_CLR_0 UL(0xFF63C40C) macro
/rk3399_ARM-atf/plat/amlogic/gxl/
H A Dgxl_def.h103 #define AML_HIU_MAILBOX_CLR_0 UL(0xDA83C40C) macro
/rk3399_ARM-atf/plat/amlogic/g12a/
H A Dg12a_def.h105 #define AML_HIU_MAILBOX_CLR_0 UL(0xFF63C40C) macro