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Searched refs:core_mmu_get_va (Results 1 – 25 of 42) sorted by relevance

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/optee_os/core/drivers/pm/imx/
H A Dsrc.c34 vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC, SRC_SIZE); in imx_get_src_gpr_arg()
41 vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC, SRC_SIZE); in imx_set_src_gpr_arg()
48 vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC, SRC_SIZE); in imx_get_src_gpr_entry()
55 vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC, SRC_SIZE); in imx_set_src_gpr_entry()
62 vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC, SRC_SIZE); in imx_src_release_secondary_core()
74 vaddr_t va = core_mmu_get_va(SRC_BASE, MEM_AREA_IO_SEC, SRC_SIZE); in imx_src_shutdown_core()
H A Dgpcv2.c25 vaddr_t va = core_mmu_get_va(GPC_BASE, MEM_AREA_IO_SEC, GPC_SIZE); in imx_gpcv2_set_core_pgc()
35 vaddr_t va = core_mmu_get_va(GPC_BASE, MEM_AREA_IO_SEC, GPC_SIZE); in imx_gpcv2_set_core1_pup_by_software()
H A Dpsci.c93 vaddr_t base = core_mmu_get_va(IOMUXC_BASE, MEM_AREA_IO_SEC, in psci_affinity_info()
/optee_os/core/drivers/
H A Dimx_snvs.c70 vaddr_t base = core_mmu_get_va(SNVS_BASE, MEM_AREA_IO_SEC, SNVS_SIZE); in is_otpmk_selected()
93 vaddr_t base = core_mmu_get_va(SNVS_BASE, MEM_AREA_IO_SEC, SNVS_SIZE); in is_mks_locked()
102 vaddr_t base = core_mmu_get_va(SNVS_BASE, MEM_AREA_IO_SEC, SNVS_SIZE); in set_mks_otpmk()
115 vaddr_t base = core_mmu_get_va(SNVS_BASE, MEM_AREA_IO_SEC, SNVS_SIZE); in is_otpmk_valid()
124 vaddr_t base = core_mmu_get_va(SNVS_BASE, MEM_AREA_IO_SEC, in snvs_get_security_cfg()
150 vaddr_t snvs = core_mmu_get_va(SNVS_BASE, MEM_AREA_IO_SEC, in snvs_get_ssm_mode()
201 vaddr_t base = core_mmu_get_va(SNVS_BASE, MEM_AREA_IO_SEC, SNVS_SIZE); in imx_snvs_shutdown()
H A Dzynqmp_csu_puf.c31 vaddr_t puf = core_mmu_get_va(ZYNQMP_CSU_PUF_BASE, MEM_AREA_IO_SEC, in zynqmp_csu_puf_regenerate()
33 vaddr_t csu = core_mmu_get_va(CSU_BASE, MEM_AREA_IO_SEC, CSU_SIZE); in zynqmp_csu_puf_regenerate()
55 vaddr_t puf = core_mmu_get_va(ZYNQMP_CSU_PUF_BASE, MEM_AREA_IO_SEC, in zynqmp_csu_puf_reset()
63 vaddr_t csu = core_mmu_get_va(CSU_BASE, MEM_AREA_IO_SEC, CSU_SIZE); in zynqmp_csu_puf_init()
H A Dzynqmp_csudma.c47 vaddr_t dma = core_mmu_get_va(CSUDMA_BASE, MEM_AREA_IO_SEC, in csudma_clear_intr()
61 vaddr_t dma = core_mmu_get_va(CSUDMA_BASE, MEM_AREA_IO_SEC, in zynqmp_csudma_sync()
85 vaddr_t dma = core_mmu_get_va(CSUDMA_BASE, MEM_AREA_IO_SEC, in zynqmp_csudma_prepare()
100 vaddr_t dma = core_mmu_get_va(CSUDMA_BASE, MEM_AREA_IO_SEC, in zynqmp_csudma_unprepare()
111 vaddr_t dma = core_mmu_get_va(CSUDMA_BASE, MEM_AREA_IO_SEC, in zynqmp_csudma_transfer()
H A Dimx_ocotp.c37 vaddr_t va = core_mmu_get_va(CCM_BASE, MEM_AREA_IO_SEC, CCM_SIZE); in ocotp_clock_enable()
44 vaddr_t va = core_mmu_get_va(CCM_BASE, MEM_AREA_IO_SEC, CCM_SIZE); in ocotp_clock_enable()
52 vaddr_t va = core_mmu_get_va(CCM_BASE, MEM_AREA_IO_SEC, CCM_SIZE); in ocotp_clock_enable()
257 g_base_addr = core_mmu_get_va(OCOTP_BASE, MEM_AREA_IO_SEC, OCOTP_SIZE); in imx_ocotp_init()
H A Dzynqmp_csu_aes.c48 vaddr_t aes = core_mmu_get_va(ZYNQMP_CSU_AES_BASE, MEM_AREA_IO_SEC, in aes_wait()
209 vaddr_t aes = core_mmu_get_va(ZYNQMP_CSU_AES_BASE, MEM_AREA_IO_SEC, in aes_prepare_op()
211 vaddr_t csu = core_mmu_get_va(CSU_BASE, MEM_AREA_IO_SEC, CSU_SIZE); in aes_prepare_op()
251 vaddr_t aes = core_mmu_get_va(ZYNQMP_CSU_AES_BASE, MEM_AREA_IO_SEC, in aes_done_op()
H A Dimx_scu.c22 vaddr_t scu_base = core_mmu_get_va(SCU_BASE, MEM_AREA_IO_SEC, in scu_init()
H A Dimx_caam.c42 core_mmu_get_va(CAAM_BASE, MEM_AREA_IO_SEC, in init_caam()
/optee_os/core/arch/arm/plat-rzn1/
H A Dmain.c58 tza_init_reg = core_mmu_get_va(FW_STATIC_TZA_INIT, MEM_AREA_IO_SEC, in rzn1_tz_init()
60 tza_targ_reg = core_mmu_get_va(FW_STATIC_TZA_TARG, MEM_AREA_IO_SEC, in rzn1_tz_init()
84 cm3_pwrctrl_reg = core_mmu_get_va(SYSCTRL_PWRCTRL_CM3, MEM_AREA_IO_SEC, in rzn1_cm3_start()
86 cm3_pwrstat_reg = core_mmu_get_va(SYSCTRL_PWRSTAT_CM3, MEM_AREA_IO_SEC, in rzn1_cm3_start()
H A Dpsci.c45 vaddr_t sctl_va = core_mmu_get_va(SYSCTRL_BOOTADDR_REG, in psci_cpu_on()
78 io_setbits32(core_mmu_get_va(SYSCTRL_REG_RSTEN, MEM_AREA_IO_SEC, in psci_system_reset()
83 io_setbits32(core_mmu_get_va(SYSCTRL_REG_RSTCTRL, MEM_AREA_IO_SEC, in psci_system_reset()
/optee_os/core/arch/arm/plat-k3/drivers/
H A Dmailbox.c102 mailbox_rx_base = core_mmu_get_va(TI_MAILBOX_RX_BASE, in ti_sci_transport_init()
108 mailbox_tx_base = core_mmu_get_va(TI_MAILBOX_TX_BASE, in ti_sci_transport_init()
114 mailbox_tx_sram_va = core_mmu_get_va(MAILBOX_TX_START_REGION, in ti_sci_transport_init()
120 mailbox_rx_sram_va = core_mmu_get_va(MAILBOX_RX_START_REGION, in ti_sci_transport_init()
H A Dsec_proxy.c255 thread->data = core_mmu_get_va(target_data, MEM_AREA_IO_SEC, in ti_sci_transport_init()
260 thread->scfg = core_mmu_get_va(cfg_scfg, MEM_AREA_IO_SEC, in ti_sci_transport_init()
265 thread->rt = core_mmu_get_va(cfg_rt, MEM_AREA_IO_SEC, in ti_sci_transport_init()
278 thread->data = core_mmu_get_va(target_data, MEM_AREA_IO_SEC, in ti_sci_transport_init()
283 thread->scfg = core_mmu_get_va(cfg_scfg, MEM_AREA_IO_SEC, in ti_sci_transport_init()
288 thread->rt = core_mmu_get_va(cfg_rt, MEM_AREA_IO_SEC, in ti_sci_transport_init()
/optee_os/core/arch/arm/plat-hisilicon/
H A Dpsci.c50 vaddr_t sysctrl = core_mmu_get_va(SYS_CTRL_BASE, MEM_AREA_IO_SEC, in psci_system_reset()
67 vaddr_t bootsram = core_mmu_get_va(BOOTSRAM_BASE, MEM_AREA_IO_SEC, in psci_cpu_on()
69 vaddr_t crg = core_mmu_get_va(CPU_CRG_BASE, MEM_AREA_IO_SEC, in psci_cpu_on()
/optee_os/core/arch/arm/plat-hikey/
H A Dmain.c56 vaddr_t peri_base = core_mmu_get_va(PERI_BASE, MEM_AREA_IO_NSEC, in spi_init()
58 vaddr_t pmx0_base = core_mmu_get_va(PMX0_BASE, MEM_AREA_IO_NSEC, in spi_init()
60 vaddr_t pmx1_base = core_mmu_get_va(PMX1_BASE, MEM_AREA_IO_NSEC, in spi_init()
124 vaddr_t pmussi_base = core_mmu_get_va(PMUSSI_BASE, MEM_AREA_IO_NSEC, in peripherals_init()
H A Dspi_test.c23 vaddr_t gpio6_base = core_mmu_get_va(GPIO6_BASE, MEM_AREA_IO_NSEC, in spi_cs_callback()
25 vaddr_t spi_base = core_mmu_get_va(SPI_BASE, MEM_AREA_IO_NSEC, in spi_cs_callback()
50 vaddr_t pmx0_base = core_mmu_get_va(PMX0_BASE, MEM_AREA_IO_NSEC, in spi_set_cs_mux()
71 vaddr_t spi_base = core_mmu_get_va(SPI_BASE, MEM_AREA_IO_NSEC, in spi_test_with_manual_cs_control()
160 vaddr_t spi_base = core_mmu_get_va(SPI_BASE, MEM_AREA_IO_NSEC, in spi_test_with_registered_cs_cb()
207 vaddr_t gpio6_base = core_mmu_get_va(GPIO6_BASE, MEM_AREA_IO_NSEC, in spi_test_with_builtin_cs_control()
209 vaddr_t spi_base = core_mmu_get_va(SPI_BASE, MEM_AREA_IO_NSEC, in spi_test_with_builtin_cs_control()
/optee_os/core/arch/arm/plat-imx/
H A Dtzc380.c56 addr[0] = core_mmu_get_va(TZASC_BASE, MEM_AREA_IO_SEC, 1); in imx_configure_tzasc()
61 addr[1] = core_mmu_get_va(TZASC2_BASE, MEM_AREA_IO_SEC, 1); in imx_configure_tzasc()
H A Dimx_pl310.c84 return core_mmu_get_va(PL310_BASE, MEM_AREA_IO_SEC, 1); in pl310_base()
89 return core_mmu_get_va(PL310_BASE, MEM_AREA_IO_NSEC, 1); in pl310_nsbase()
H A Dimx-common.c32 addr = core_mmu_get_va(ANATOP_BASE, MEM_AREA_IO_SEC, 0x1000); in imx_get_digprog()
43 addr = core_mmu_get_va(OCOTP_BASE, MEM_AREA_IO_SEC, OCOTP_SIZE); in imx_get_digprog()
/optee_os/core/arch/arm/sm/
H A Dpm.c48 arm_cl2_cleanbyway(core_mmu_get_va(PL310_BASE, MEM_AREA_IO_SEC, 1)); in sm_pm_cpu_suspend_save()
/optee_os/core/drivers/crypto/aspeed/
H A Dcrypto_ast2600.c28 scu_virt = core_mmu_get_va(SCU_BASE, MEM_AREA_IO_NSEC, SMALL_PAGE_SIZE); in crypto_ast2600_init()
/optee_os/core/arch/arm/plat-zynqmp/
H A Dmain.c93 vaddr_t csu = core_mmu_get_va(CSU_BASE, MEM_AREA_IO_SEC, CSU_SIZE); in plat_rpmb_key_is_ready()
/optee_os/core/arch/arm/plat-aspeed/
H A Dplatform_ast2600.c85 ahbc_virt = core_mmu_get_va(AHBC_BASE, in plat_primary_init_early()
/optee_os/core/include/mm/
H A Dcore_memprot.h102 vaddr_t core_mmu_get_va(paddr_t pa, enum teecore_memtypes type, size_t len);

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