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Searched refs:SHIFT_U32 (Results 1 – 25 of 110) sorted by relevance

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/optee_os/core/include/drivers/sam/
H A Dat91_ddr.h15 #define AT91_DDRSDRC_MODE SHIFT_U32(0x7, 0)
27 #define AT91_DDRSDRC_COUNT SHIFT_U32(0xfff, 0)
32 #define AT91_DDRSDRC_NC SHIFT_U32(3, 0)
33 #define AT91_DDRSDRC_NC_SDR8 SHIFT_U32(0, 0)
35 #define AT91_DDRSDRC_NC_SDR10 SHIFT_U32(2, 0)
36 #define AT91_DDRSDRC_NC_SDR11 SHIFT_U32(3, 0)
37 #define AT91_DDRSDRC_NC_DDR9 SHIFT_U32(0, 0)
39 #define AT91_DDRSDRC_NC_DDR11 SHIFT_U32(2, 0)
40 #define AT91_DDRSDRC_NC_DDR12 SHIFT_U32(3, 0)
42 #define AT91_DDRSDRC_NR SHIFT_U32(3, 2)
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H A Dsama7-ddr.h67 #define UDDRC_STAT_SELFREF_TYPE_DIS SHIFT_U32(0, 4)
69 #define UDDRC_STAT_SELFREF_TYPE_PHY SHIFT_U32(1, 4)
73 #define UDDRC_STAT_SELFREF_TYPE_SW SHIFT_U32(2, 4)
75 #define UDDRC_STAT_SELFREF_TYPE_AUTO SHIFT_U32(3, 4)
/optee_os/core/arch/arm/plat-imx/registers/
H A Dimx6-crm.h90 SHIFT_U32(0x3F, BS_CCM_CCR_REG_BYPASS_COUNT)
92 #define BM_CCM_CCR_WB_COUNT SHIFT_U32(0x7, BS_CCM_CCR_WB_COUNT)
94 #define BM_CCM_CCR_OSCNT SHIFT_U32(0xFF, BS_CCM_CCR_OSCNT)
95 #define CCM_CCR_COSC_EN SHIFT_U32((1 << 12), BS_CCM_CCR_OSCNT)
135 #define BM_CCM_CACRR_ARM_PODF SHIFT_U32(0x7, BS_CCM_CACRR_ARM_PODF)
140 SHIFT_U32(0x7, BS_CCM_CBCDR_PERIPH_CLK2_PODF)
147 SHIFT_U32(0x7, BS_CCM_CBCDR_MMDC_CH0_PODF)
149 #define BM_CCM_CBCDR_AXI_PODF SHIFT_U32(0x7, BS_CCM_CBCDR_AXI_PODF)
151 #define BM_CCM_CBCDR_AHB_PODF SHIFT_U32(0x7, BS_CCM_CBCDR_AHB_PODF)
153 #define BM_CCM_CBCDR_IPG_PODF SHIFT_U32(0x3, BS_CCM_CBCDR_IPG_PODF)
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H A Dimx8m-crm.h19 SHIFT_U32(0x3, BS_CCM_CCGRx_SETTING(idx))
21 SHIFT_U32(0, BS_CCM_CCGRx_SETTING(idx))
25 SHIFT_U32(0x2, BS_CCM_CCGRx_SETTING(idx))
27 SHIFT_U32(0x3, BS_CCM_CCGRx_SETTING(idx))
H A Dimx6-dcp.h92 #define DCP_CONTROL1_HASH_SELECT_SHA256 SHIFT_U32(2, 16)
94 #define DCP_CONTROL1_HASH_SELECT_SHA1 SHIFT_U32(0, 16)
96 #define DCP_CONTROL1_CIPHER_MODE_ECB SHIFT_U32(0, 4)
98 #define DCP_CONTROL1_KEY_SELECT_OTP_CRYPTO SHIFT_U32(0xfe, 8)
/optee_os/core/drivers/crypto/caam/hal/common/registers/
H A Drng_regs.h20 #define BM_TRNG_MCTL_SAMP_MODE SHIFT_U32(0x3, 0)
22 #define TRNG_MCTL_SAMP_MODE_RAW_ES_SC SHIFT_U32(1, 0)
26 #define BM_TRNG_SDCTL_ENT_DLY SHIFT_U32(0xFFFF, 16)
28 #define TRNG_SDCTL_ENT_DLY(val) SHIFT_U32(((val) & 0xFFFF), 16)
45 #define BM_TRNG_RTSCMISC_RTY_CNT SHIFT_U32(0xF, 16)
46 #define TRNG_RTSCMISC_RTY_CNT(val) SHIFT_U32(((val) & (0xF)), 16)
47 #define BM_TRNG_RTSCMISC_LRUN_MAX SHIFT_U32(0xFF, 0)
48 #define TRNG_RTSCMISC_LRUN_MAX(val) SHIFT_U32(((val) & (0xFF)), 0)
52 #define BM_TRNG_RTPKRRNG_PKR_RNG SHIFT_U32(0xFFFF, 0)
53 #define TRNG_RTPKRRNG_PKR_RNG(val) SHIFT_U32(((val) & (0xFFFF)), 0)
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H A Dversion_regs.h14 #define BM_CTPR_MS_RNG_I SHIFT_U32(0x7, 8)
23 #define BM_SMVID_MS_MAX_NPAG SHIFT_U32(0x3FF, 16)
25 #define BM_SMVID_MS_NPRT SHIFT_U32(0xF, 12)
29 #define BM_SMVID_LS_PSIZ SHIFT_U32(0x7, 16)
34 #define BM_CCBVID_CAAM_ERA SHIFT_U32(0xFF, 24)
39 #define BM_CHAVID_LS_RNGVID SHIFT_U32(0xF, 16)
41 #define BM_CHAVID_LS_MDVID SHIFT_U32(0xF, 12)
43 #define CHAVID_LS_MDVID_LP256 SHIFT_U32(0, 12)
47 #define BM_CHANUM_MS_JRNUM SHIFT_U32(0xF, 28)
51 #define BM_CHANUM_LS_PKNUM SHIFT_U32(0xF, 28)
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H A Djr_regs.h42 #define BM_JRX_JRINTR_HALT SHIFT_U32(0x3, 2)
43 #define JRINTR_HALT_RESUME SHIFT_U32(0x2, 2)
44 #define JRINTR_HALT_ONGOING SHIFT_U32(0x1, 2)
45 #define JRINTR_HALT_DONE SHIFT_U32(0x2, 2)
50 #define JRX_JRCFGR_LS_ICTT(val) SHIFT_U32((val) & 0xFFFF, 16)
51 #define JRX_JRCFGR_LS_ICDCT(val) SHIFT_U32((val) & 0xFF, 8)
H A Dsm_regs.h12 #define SM_SMAPR_GRP1(perm) SHIFT_U32((perm) & 0xF, 0)
13 #define SM_SMAPR_GRP2(perm) SHIFT_U32((perm) & 0xF, 4)
24 #define SM_SMCR_PAGE(page) SHIFT_U32((page) & UINT16_MAX, 16)
25 #define SM_SMCR_PRTN(prtn) SHIFT_U32((prtn) & 0xF, 8)
26 #define SM_SMCR_CMD(cmd) SHIFT_U32((cmd) & 0xF, 0)
/optee_os/core/drivers/crypto/caam/include/
H A Dcaam_desc_defines.h15 #define CMD_TYPE(cmd) SHIFT_U32((cmd) & 0x1F, 27)
16 #define GET_CMD_TYPE(op) ((op) & (SHIFT_U32(0x1F, 27)))
17 #define CMD_CLASS(val) SHIFT_U32((val) & 0x3, 25)
35 #define HDR_JD_START_IDX(line) SHIFT_U32((line) & 0x3F, 16)
38 #define HDR_JD_DESCLEN(len) SHIFT_U32((len) & 0x7F, 0)
47 #define KEY_DEST(val) SHIFT_U32((KEY_DEST_##val) & 0x3, 16)
57 #define KEY_LENGTH(len) SHIFT_U32((len) & 0x3FF, 0)
65 #define LOAD_DST(reg) SHIFT_U32((reg) & 0x7F, 16)
68 #define LOAD_OFFSET(off) SHIFT_U32((off) & 0xFF, 8)
71 #define LOAD_LENGTH(len) SHIFT_U32((len) & 0xFF, 0)
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H A Dcaam_jr_status.h13 #define BM_JRSTA_SRC SHIFT_U32(0xF, 28)
16 #define JRSTA_SRC(src) SHIFT_U32(JRSTA_SRC_##src, 28)
25 #define JRSTA_CCB_GET_ERR(status) ((status) & SHIFT_U32(0xFF, 0))
26 #define JRSTA_CCB_CHAID_RNG SHIFT_U32(0x5, 4)
27 #define JRSTA_CCB_ERRID_HW SHIFT_U32(0xB, 0)
28 #define JRSTA_DECO_ERRID_FORMAT SHIFT_U32(0x88, 0)
29 #define JRSTA_DECO_INV_SIGNATURE SHIFT_U32(0x86, 0)
H A Dcaam_desc_ccb_defines.h25 #define NFIFO_CLASS(cla) SHIFT_U32(NFIFO_CLASS_##cla & 0x3, 30)
34 #define NFIFO_STYPE(src) SHIFT_U32(NFIFO_STYPE_##src & 0x3, 24)
38 #define NFIFO_DTYPE(data) SHIFT_U32(NFIFO_DTYPE_##data & 0xF, 20)
44 #define NFIFO_PTYPE(pad) SHIFT_U32(NFIFO_PTYPE_##pad & 0x7, 16)
48 #define NFIFO_DATA_LENGTH(len) SHIFT_U32((len) & 0xFFF, 0)
49 #define NFIFO_PAD_LENGTH(len) SHIFT_U32((len) & 0x7F, 0)
/optee_os/core/drivers/
H A Dpl022_spi.c54 #define SSPCR0_SCR SHIFT_U32(0xFF, 8)
55 #define SSPCR0_SPH SHIFT_U32(1, 7)
56 #define SSPCR0_SPH1 SHIFT_U32(1, 7)
57 #define SSPCR0_SPH0 SHIFT_U32(0, 7)
58 #define SSPCR0_SPO SHIFT_U32(1, 6)
59 #define SSPCR0_SPO1 SHIFT_U32(1, 6)
60 #define SSPCR0_SPO0 SHIFT_U32(0, 6)
61 #define SSPCR0_FRF SHIFT_U32(3, 4)
62 #define SSPCR0_FRF_SPI SHIFT_U32(0, 4)
63 #define SSPCR0_DSS SHIFT_U32(0xFF, 0)
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/optee_os/core/drivers/clk/sam/
H A Dat91_pmc.h155 #define AT91_PMC_MCR_V2_DIV1 SHIFT_U32(0, 8)
156 #define AT91_PMC_MCR_V2_DIV2 SHIFT_U32(1, 8)
157 #define AT91_PMC_MCR_V2_DIV4 SHIFT_U32(2, 8)
158 #define AT91_PMC_MCR_V2_DIV8 SHIFT_U32(3, 8)
159 #define AT91_PMC_MCR_V2_DIV16 SHIFT_U32(4, 8)
160 #define AT91_PMC_MCR_V2_DIV32 SHIFT_U32(5, 8)
161 #define AT91_PMC_MCR_V2_DIV64 SHIFT_U32(6, 8)
162 #define AT91_PMC_MCR_V2_DIV3 SHIFT_U32(7, 8)
165 #define AT91_PMC_MCR_V2_CSS_MD_SLCK SHIFT_U32(0, 16)
166 #define AT91_PMC_MCR_V2_CSS_TD_SLCK SHIFT_U32(1, 16)
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/optee_os/core/drivers/crypto/caam/hal/imx_6_7/registers/
H A Dctrl_regs.h15 #define MCFGR_AXIPIPE(val) SHIFT_U32(val, 4)
16 #define BM_MCFGR_AXIPIPE SHIFT_U32(0xF, 4)
30 #define JRxMIDR_MS_JROWN_MID(val) SHIFT_U32((val) & 0x7, 0)
33 #define JRxMIDR_LS_NONSEQ_MID(val) SHIFT_U32((val) & 0x7, 16)
35 #define JRxMIDR_LS_SEQ_MID(val) SHIFT_U32((val) & 0x7, 0)
38 #define JRxMIDR_MS_JROWN_MID(val) SHIFT_U32((val) & 0xF, 0)
41 #define JRxMIDR_LS_NONSEQ_MID(val) SHIFT_U32((val) & 0xF, 16)
43 #define JRxMIDR_LS_SEQ_MID(val) SHIFT_U32((val) & 0xF, 0)
49 #define BM_SCFGR_MPCURVE SHIFT_U32(0xF, BS_SCFGR_MPCURVE)
/optee_os/core/drivers/crypto/caam/hal/ls/registers/
H A Dctrl_regs.h15 #define MCFGR_AXIPIPE(val) SHIFT_U32(val, 4)
16 #define BM_MCFGR_AXIPIPE SHIFT_U32(0xF, 4)
30 #define JRxMIDR_MS_JROWN_MID(val) SHIFT_U32((val) & 0x7, 0)
33 #define JRxMIDR_LS_NONSEQ_MID(val) SHIFT_U32((val) & 0x7, 16)
35 #define JRxMIDR_LS_SEQ_MID(val) SHIFT_U32((val) & 0x7, 0)
/optee_os/core/tee/
H A Duuid.c25 d->timeLow = SHIFT_U32(s[0], 24) | SHIFT_U32(s[1], 16) | in tee_uuid_from_octets()
26 SHIFT_U32(s[2], 8) | s[3]; in tee_uuid_from_octets()
27 d->timeMid = SHIFT_U32(s[4], 8) | s[5]; in tee_uuid_from_octets()
28 d->timeHiAndVersion = SHIFT_U32(s[6], 8) | s[7]; in tee_uuid_from_octets()
/optee_os/core/include/drivers/
H A Datmel_saic.h19 #define AT91_AIC_SMR_LEVEL SHIFT_U32(0, AT91_AIC_SMR_SRC_SHIFT)
20 #define AT91_AIC_SMR_NEG_EDGE SHIFT_U32(1, AT91_AIC_SMR_SRC_SHIFT)
21 #define AT91_AIC_SMR_HIGH_LEVEL SHIFT_U32(2, AT91_AIC_SMR_SRC_SHIFT)
22 #define AT91_AIC_SMR_POS_EDGE SHIFT_U32(3, AT91_AIC_SMR_SRC_SHIFT)
/optee_os/core/drivers/crypto/caam/hal/imx_8q/registers/
H A Dctrl_regs.h19 #define JRxDID_MS_PRIM_ICID(val) SHIFT_U32((val) & (0x3FF), 19)
24 #define JRxDID_MS_PRIM_DID(val) SHIFT_U32((val) & (0xF), 0)
29 #define BM_SCFGR_MPCURVE SHIFT_U32(0xF, BS_SCFGR_MPCURVE)
/optee_os/core/arch/arm/plat-stm/
H A Dplatform_config.h100 #define SCU_CPUS_MASK (SHIFT_U32(1, CFG_TEE_CORE_NB_CORE) - 1)
103 #define SCU_NSAC_INIT (SHIFT_U32(SCU_CPUS_MASK, SCU_NSAC_SCU_SHIFT) | \
104 SHIFT_U32(SCU_CPUS_MASK, SCU_NSAC_PTIMER_SHIFT) | \
105 SHIFT_U32(SCU_CPUS_MASK, SCU_NSAC_GTIMER_SHIFT))
/optee_os/core/drivers/crypto/caam/hal/imx_8ulp/registers/
H A Dctrl_regs.h24 #define JRxDID_MS_PRIM_ICID(val) SHIFT_U32(((val) & (0x3FF)), 19)
29 #define JRxDID_MS_PRIM_DID(val) SHIFT_U32(((val) & (0xF)), 0)
34 #define BM_SCFGR_MPCURVE SHIFT_U32(0xF, BS_SCFGR_MPCURVE)
/optee_os/core/drivers/crypto/caam/hal/imx_8m/registers/
H A Dctrl_regs.h24 #define JRxDID_MS_PRIM_ICID(val) SHIFT_U32(((val) & 0x3FF), 19)
29 #define JRxDID_MS_PRIM_DID(val) SHIFT_U32(((val) & 0xF), 0)
34 #define BM_SCFGR_MPCURVE SHIFT_U32(0xF, BS_SCFGR_MPCURVE)
/optee_os/core/drivers/crypto/hisilicon/
H A Dsec_pbkdf2.c34 sqe->type_auth_cipher |= SHIFT_U32(AUTH_MAC_CALCULATE, SEC_AUTH_OFFSET); in sec_pbkdf2_fill_sqe()
35 sqe->sds_sa_type = SHIFT_U32(SCENE_PBKDF2, SEC_SCENE_OFFSET); in sec_pbkdf2_fill_sqe()
37 sqe->type2.mac_key_alg = SHIFT_U32(pbkdf2_msg->derive_type, in sec_pbkdf2_fill_sqe()
41 sqe->type2.mac_key_alg |= SHIFT_U32(0x1, SEC_AKEY_OFFSET); in sec_pbkdf2_fill_sqe()
49 sqe->huk_ci_key = SHIFT_U32(SEC_HUK_ENABLE, SEC_HUK_OFFSET); in sec_pbkdf2_fill_sqe()
80 sqe->bd_param = BD_TYPE3 | SHIFT_U32(SCENE_PBKDF2, SEC_SCENE_OFFSET_V3); in sec_pbkdf2_fill_bd3_sqe()
82 sqe->auth_mac_key |= SHIFT_U32(pbkdf2_msg->derive_type, in sec_pbkdf2_fill_bd3_sqe()
85 sqe->auth_mac_key |= SHIFT_U32(0x1, SEC_AKEY_OFFSET_V3); in sec_pbkdf2_fill_bd3_sqe()
86 sqe->auth_mac_key |= SHIFT_U32(0x1, SEC_MAC_OFFSET_V3); in sec_pbkdf2_fill_bd3_sqe()
91 sqe->pbkdf2_scene.pass_word_dk_len |= SHIFT_U32(pbkdf2_msg->out_len, in sec_pbkdf2_fill_bd3_sqe()
[all …]
/optee_os/core/arch/arm/plat-rockchip/
H A Dcru.h31 #define CORE_SOFT_RESET(core) SHIFT_U32(0x100010, (core))
32 #define CORE_SOFT_RELEASE(core) SHIFT_U32(0x100000, (core))
33 #define CORE_HELD_IN_RESET(core) SHIFT_U32(0x000010, (core))
/optee_os/core/arch/arm/include/
H A Dffa.h163 #define FFA_MEMORY_REGION_TRANSACTION_TYPE_SHARE SHIFT_U32(1, 3)
165 #define FFA_MEMORY_REGION_TRANSACTION_TYPE_LEND SHIFT_U32(2, 3)
204 #define FFA_PART_PROP_IS_PE_ID SHIFT_U32(0, 4)
205 #define FFA_PART_PROP_IS_SEPID_INDEP SHIFT_U32(1, 4)
206 #define FFA_PART_PROP_IS_SEPID_DEP SHIFT_U32(2, 4)
207 #define FFA_PART_PROP_IS_AUX_ID SHIFT_U32(3, 4)
254 #define FFA_MEMORY_TRANSACTION_TYPE_SHARE SHIFT_U32(1, 3)
255 #define FFA_MEMORY_TRANSACTION_TYPE_LEND SHIFT_U32(2, 3)
256 #define FFA_MEMORY_TRANSACTION_TYPE_DONATE SHIFT_U32(3, 3)

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