Searched refs:PLL1_ID (Results 1 – 3 of 3) sorted by relevance
| /optee_os/core/drivers/clk/ |
| H A D | clk-stm32mp13.c | 859 PLL1_ID, enumerator
916 CLK_PLL_CFG(PLL1_ID, PLL_2000, GATE_PLL1, MUX_PLL12, RCC_PLL1CR),
1360 const int plls[] = { PLL1_ID, PLL3_ID, PLL4_ID }; in stm32_clk_pll_configure()
1577 for (i = PLL1_ID; i < pdata->npll; i++) { in stm32_clk_parse_fdt_all_pll()
1837 const struct stm32_clk_pll *pll = clk_stm32_pll_data(PLL1_ID); in clk_stm32_pll1_set_rate()
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| H A D | clk-stm32mp21.c | 962 PLL1_ID, enumerator
996 CLK_PLL_CFG(PLL1_ID, GATE_PLL1, MUX_MUXSEL5, 0),
1616 if (i == PLL1_ID) in stm32_clk_pll_configure()
2139 clk_stm32_pll1_init(priv, PLL1_ID, pll_conf); in clk_stm32_pll1_set_rate()
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| H A D | clk-stm32mp25.c | 980 PLL1_ID, enumerator
1014 CLK_PLL_CFG(PLL1_ID, GATE_PLL1, MUX_MUXSEL5, 0),
1620 if (i == PLL1_ID) in stm32_clk_pll_configure()
2132 clk_stm32_pll1_init(priv, PLL1_ID, pll_conf); in clk_stm32_pll1_set_rate()
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