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Searched refs:pup (Results 1 – 16 of 16) sorted by relevance

/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_pbs.c52 u32 pup = 0, bit = 0, if_id = 0, all_lock = 0, cs_num = 0; in ddr3_tip_pbs() local
91 for (pup = 0; pup < tm->num_of_bus_per_interface; pup++) { in ddr3_tip_pbs()
92 VALIDATE_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_pbs()
95 min_adll_per_pup[if_id][pup] = in ddr3_tip_pbs()
97 pup_state[if_id][pup] = 0x3; in ddr3_tip_pbs()
98 adll_shift_lock[if_id][pup] = 1; in ddr3_tip_pbs()
99 max_adll_per_pup[if_id][pup] = 0x0; in ddr3_tip_pbs()
104 for (pup = 0; pup < tm->num_of_bus_per_interface; pup++) { in ddr3_tip_pbs()
105 VALIDATE_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_pbs()
111 bit + pup * BUS_WIDTH_IN_BITS], in ddr3_tip_pbs()
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H A Dddr3_training_hw_algo.c168 u32 pup = 0, if_id = 0, num_pup = 0, rep = 0; in ddr3_tip_vref() local
189 for (pup = 0; in ddr3_tip_vref()
190 pup < tm->num_of_bus_per_interface; pup++) { in ddr3_tip_vref()
191 current_vref[pup][if_id] = 0; in ddr3_tip_vref()
192 last_vref[pup][if_id] = 0; in ddr3_tip_vref()
193 lim_vref[pup][if_id] = 0; in ddr3_tip_vref()
194 current_valid_window[pup][if_id] = 0; in ddr3_tip_vref()
195 last_valid_window[pup][if_id] = 0; in ddr3_tip_vref()
196 if (vref_window_size[if_id][pup] > in ddr3_tip_vref()
198 pup_st[pup][if_id] = VREF_CONVERGE; in ddr3_tip_vref()
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H A Dddr3_debug.c1285 u32 pup = 0, start_pup = 0, end_pup = 0; in ddr3_tip_run_sweep_test() local
1316 for (pup = start_pup; pup <= end_pup; pup++) { in ddr3_tip_run_sweep_test()
1317 ctrl_sweepres[adll][if_id][pup] = in ddr3_tip_run_sweep_test()
1334 for (pup = start_pup; pup <= end_pup; pup++) { in ddr3_tip_run_sweep_test()
1340 pup_access, pup, DDR_PHY_DATA, in ddr3_tip_run_sweep_test()
1352 ctrl_sweepres[adll][if_id][pup] in ddr3_tip_run_sweep_test()
1361 pup, in ddr3_tip_run_sweep_test()
1367 + pup])); in ddr3_tip_run_sweep_test()
1377 for (pup = start_pup; pup <= end_pup; pup++) { in ddr3_tip_run_sweep_test()
1378 VALIDATE_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_run_sweep_test()
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/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_dqs.c69 int ddr3_check_window_limits(u32 pup, int high_limit, int low_limit, int is_tx,
298 u32 victim_dq, pup, tmp; in ddr3_find_adll_limits() local
327 for (pup = 0; pup < max_pup; pup++) { in ddr3_find_adll_limits()
328 centralization_low_limit[pup] = ADLL_MIN; in ddr3_find_adll_limits()
329 centralization_high_limit[pup] = ADLL_MAX; in ddr3_find_adll_limits()
343 for (pup = 0; pup < max_pup; pup++) in ddr3_find_adll_limits()
344 pup_mask |= (1 << pup); in ddr3_find_adll_limits()
346 for (pup = 0; pup < max_pup; pup++) { in ddr3_find_adll_limits()
348 analog_pbs_sum[pup][dq][0] = adll_start_val; in ddr3_find_adll_limits()
349 analog_pbs_sum[pup][dq][1] = adll_end_val; in ddr3_find_adll_limits()
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H A Dddr3_pbs.c67 static void ddr3_pbs_write_pup_dqs_reg(u32 cs, u32 pup, u32 dqs_delay);
97 u32 pup, dq, pups, cur_max_pup, valid_pup, reg; in ddr3_pbs_tx() local
125 for (pup = 0; pup < pups; pup++) { in ddr3_pbs_tx()
127 skew_sum_array[pup][dq] = 0; in ddr3_pbs_tx()
173 for (pup = 0; pup < cur_max_pup; pup++) { in ddr3_pbs_tx()
176 pup + ecc * in ddr3_pbs_tx()
204 pbs_dq_mapping[pup * in ddr3_pbs_tx()
245 for (pup = 0; pup < cur_max_pup; pup++) { in ddr3_pbs_tx()
251 DEBUG_PBS_D((pup + (ecc * ECC_PUP)), 1); in ddr3_pbs_tx()
266 [((pup) * DQ_NUM) + in ddr3_pbs_tx()
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H A Dddr3_write_leveling.c50 static void ddr3_write_ctrl_pup_reg(int bc_acc, u32 pup, u32 reg_addr,
67 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
109 for (pup = 0; in ddr3_write_leveling_hw()
110 pup < dram_info->num_of_total_pups; in ddr3_write_leveling_hw()
111 pup++) { in ddr3_write_leveling_hw()
112 if (pup == dram_info->num_of_std_pups in ddr3_write_leveling_hw()
114 pup = ECC_PUP; in ddr3_write_leveling_hw()
117 pup); in ddr3_write_leveling_hw()
122 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_hw()
123 dram_info->wl_val[cs][pup][D] = delay; in ddr3_write_leveling_hw()
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H A Dddr3_read_leveling.c92 u32 delay, phase, pup, cs; in ddr3_read_leveling_hw() local
100 for (pup = 0; in ddr3_read_leveling_hw()
101 pup < dram_info->num_of_total_pups; in ddr3_read_leveling_hw()
102 pup++) { in ddr3_read_leveling_hw()
103 if (pup == dram_info->num_of_std_pups in ddr3_read_leveling_hw()
105 pup = ECC_PUP; in ddr3_read_leveling_hw()
108 pup); in ddr3_read_leveling_hw()
112 dram_info->rl_val[cs][pup][P] = phase; in ddr3_read_leveling_hw()
117 dram_info->rl_val[cs][pup][D] = delay; in ddr3_read_leveling_hw()
118 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
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H A Dddr3_sdram.c92 static void compare_pattern_v1(u32 uj, u32 *pup, u32 *pattern, in compare_pattern_v1() argument
101 if (((sdram_data[uj]) != (pattern[uj])) && (*pup != 0xFF)) { in compare_pattern_v1()
108 *pup |= (1 << (uk + (PUP_NUM_32BIT * in compare_pattern_v1()
130 static void compare_pattern_v2(u32 uj, u32 *pup, u32 *pattern) in compare_pattern_v2() argument
137 if (((sdram_data[uj]) != (pattern[uj])) && (*pup != 0x3)) { in compare_pattern_v2()
144 *pup |= (1 << (uk % PUP_NUM_16BIT)); in compare_pattern_v2()
226 u32 pup = 0; in ddr3_sdram_dm_compare() local
240 compare_pattern_v1(uj, &pup, pattern, pup_groups, 0); in ddr3_sdram_dm_compare()
259 *new_locked_pup |= pup; in ddr3_sdram_dm_compare()
292 u32 ui, dq, pup; in ddr3_sdram_pbs_compare() local
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H A Dddr3_hw_training.c548 void ddr3_write_pup_reg(u32 mode, u32 cs, u32 pup, u32 phase, u32 delay) in ddr3_write_pup_reg() argument
552 if (pup == PUP_BC) in ddr3_write_pup_reg()
555 reg |= (pup << REG_PHY_PUP_OFFS); in ddr3_write_pup_reg()
576 if (pup == PUP_BC) in ddr3_write_pup_reg()
579 reg |= (pup << REG_PHY_PUP_OFFS); in ddr3_write_pup_reg()
598 u32 ddr3_read_pup_reg(u32 mode, u32 cs, u32 pup) in ddr3_read_pup_reg() argument
602 reg = (pup << REG_PHY_PUP_OFFS) | in ddr3_read_pup_reg()
698 u32 val, pup, tmp_cs, cs, i, dq; in ddr3_save_training() local
719 for (pup = 0; pup < dram_info->num_of_total_pups; in ddr3_save_training()
720 pup++) { in ddr3_save_training()
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H A Dddr3_hw_training.h327 void ddr3_write_pup_reg(u32 mode, u32 cs, u32 pup, u32 phase, u32 delay);
328 u32 ddr3_read_pup_reg(u32 mode, u32 cs, u32 pup);
/OK3568_Linux_fs/kernel/arch/arm/mach-s3c/
H A Dgpio-samsung.c45 u32 pup; in samsung_gpio_setpull_updown() local
47 pup = __raw_readl(reg); in samsung_gpio_setpull_updown()
48 pup &= ~(3 << shift); in samsung_gpio_setpull_updown()
49 pup |= pull << shift; in samsung_gpio_setpull_updown()
50 __raw_writel(pup, reg); in samsung_gpio_setpull_updown()
60 u32 pup = __raw_readl(reg); in samsung_gpio_getpull_updown() local
62 pup >>= shift; in samsung_gpio_getpull_updown()
63 pup &= 0x3; in samsung_gpio_getpull_updown()
65 return (__force samsung_gpio_pull_t)pup; in samsung_gpio_getpull_updown()
113 u32 pup = __raw_readl(reg); in s3c24xx_gpio_setpull_1() local
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/OK3568_Linux_fs/kernel/include/linux/
H A Dhp_sdc.h278 hp_sdc_irqhook *timer, *reg, *hil, *pup, *cooked; member
/OK3568_Linux_fs/kernel/drivers/input/serio/
H A Dhp_sdc.c258 if (hp_sdc.pup != NULL) in hp_sdc_isr()
259 hp_sdc.pup(irq, dev_id, status, data); in hp_sdc_isr()
842 hp_sdc.pup = NULL; in hp_sdc_init()
/OK3568_Linux_fs/buildroot/system/skeleton/etc/
H A Dprotocols16 pup 12 PUP # PARC universal packet protocol
/OK3568_Linux_fs/kernel/Documentation/admin-guide/
H A Ddevices.txt660 38 = /dev/inet/pup
673 /dev/pup -> /dev/inet/pup
/OK3568_Linux_fs/recovery/
HDrootfs.cpio.gz107070100A8AEB0000041ED0000000000000000000000116841B48100000000000000FD0000000200000000000000000000000200000000.�07070100A8B07C000081A40000000000000000000000016841263500000000000000FD0000000200000000000000000000000900000000.gitkeep��07070100A8B07D000081A40000000000000000000000016841263500000000000000FD0000000200000000000000000000000B00000000.skip_fsck����07070100A8AEB10000A1FF0000000000000000000000016841B0B600000007000000FD0000000200000000000000000000000400000000bin���usr/bin�07070100A8B07E000081A400000000000000000000000168412635000001CC000000FD0000000200000000000000000000001100000000busybox. ...