Searched refs:pllinfo (Results 1 – 7 of 7) sorted by relevance
94 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid]; in clock_ll_read_pll() local103 *divm = (data >> pllinfo->m_shift) & pllinfo->m_mask; in clock_ll_read_pll()104 *divn = (data >> pllinfo->n_shift) & pllinfo->n_mask; in clock_ll_read_pll()105 *divp = (data >> pllinfo->p_shift) & pllinfo->p_mask; in clock_ll_read_pll()108 *cpcon = (data >> pllinfo->kcp_shift) & pllinfo->kcp_mask; in clock_ll_read_pll()109 *lfcon = (data >> pllinfo->kvco_shift) & pllinfo->kvco_mask; in clock_ll_read_pll()118 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid]; in clock_start_pll() local143 misc_data &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift); in clock_start_pll()144 misc_data |= cpcon << pllinfo->kcp_shift; in clock_start_pll()145 misc_data &= ~(pllinfo->kvco_mask << pllinfo->kvco_shift); in clock_start_pll()[all …]
174 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU]; in pllx_set_rate() local188 reg = PLL_BYPASS_MASK | (divm << pllinfo->m_shift); in pllx_set_rate()189 reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift); in pllx_set_rate()194 reg = (cpcon << pllinfo->kcp_shift); in pllx_set_rate()215 if (pllinfo->lock_ena < 32) in pllx_set_rate()216 reg |= (1 << pllinfo->lock_ena); in pllx_set_rate()
659 struct clk_pll_info *pllinfo; in clock_early_init() local665 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()702 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()703 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()707 pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY]; in clock_early_init()708 data = (12 << pllinfo->kcp_shift) | (1 << pllinfo->kvco_shift); in clock_early_init()709 data |= (1 << PLLD_CLKENABLE) | (1 << pllinfo->lock_ena); in clock_early_init()
55 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU]; in enable_cpu_clocks() local63 } while ((reg & (1 << pllinfo->lock_det)) == 0); in enable_cpu_clocks()
839 struct clk_pll_info *pllinfo; in clock_early_init() local845 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()882 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; in clock_early_init()883 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena)); in clock_early_init()887 pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY]; in clock_early_init()888 data = (12 << pllinfo->kcp_shift) | (1 << pllinfo->kvco_shift); in clock_early_init()889 data |= (1 << PLLD_CLKENABLE) | (1 << pllinfo->lock_ena); in clock_early_init()
48 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU]; in enable_cpu_clocks() local57 } while ((reg & (1 << pllinfo->lock_det)) == 0); in enable_cpu_clocks()
974 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY]; in clock_early_init() local1029 data = (1 << PLLD_ENABLE_CLK) | (1 << pllinfo->lock_ena); in clock_early_init()