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Searched refs:mmGRBM_GFX_CNTL (Results 1 – 11 of 11) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_1_offset.h74 #define mmGRBM_GFX_CNTL … macro
H A Dgc_9_0_offset.h83 #define mmGRBM_GFX_CNTL … macro
H A Dgc_9_2_1_offset.h81 #define mmGRBM_GFX_CNTL … macro
H A Dgc_9_1_offset.h83 #define mmGRBM_GFX_CNTL … macro
H A Dgc_10_1_0_offset.h2089 #define mmGRBM_GFX_CNTL … macro
H A Dgc_10_3_0_offset.h2164 #define mmGRBM_GFX_CNTL … macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Dsoc15_common.h109 … uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; \
H A Dnv.c156 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); in nv_grbm_select()
H A Dsoc15.c267 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); in soc15_grbm_select()
H A Dgfx_v10_0.c1385 grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; in gfx_v10_rlcg_wreg()
5843 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); in gfx_v10_0_cp_gfx_switch_pipe()
5846 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); in gfx_v10_0_cp_gfx_switch_pipe()
H A Dgfx_v9_0.c755 grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; in gfx_v9_0_rlcg_wreg()