Searched refs:mainclk_hz (Results 1 – 4 of 4) sorted by relevance
10 u32 mainclk_hz; /* main input clock frequency of PSC */ member
104 u32 mainclk_hz = hw->pdata->mainclk_hz; in au1550_spi_baudcfg() local108 brg = mainclk_hz / speed_hz / (4 << div); in au1550_spi_baudcfg()875 master->max_speed_hz = hw->pdata->mainclk_hz / min_div; in au1550_spi_probe()877 hw->pdata->mainclk_hz / (max_div + 1) + 1; in au1550_spi_probe()
269 .mainclk_hz = 48000000, /* PSC0 clock: max. 2.4MHz SPI clk */601 clk_set_rate(c, db1550_spi_platdata.mainclk_hz); in db1550_dev_setup()
698 .mainclk_hz = 50000000, /* PSC0 clock */