Home
last modified time | relevance | path

Searched refs:htotal_pw (Results 1 – 8 of 8) sorted by relevance

/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A Drockchip_vop_reg.c92 .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
352 .htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
460 .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
529 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
641 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
745 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
831 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
H A Drockchip_vop.h245 struct vop_reg htotal_pw; member
H A Drockchip_vop.c463 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); in rockchip_vop_init()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/
H A Drockchip_vop_reg.c259 .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
1026 .htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
1266 .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
1388 .htotal_pw = VOP_REG(RK3066_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
1537 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
1688 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
1788 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
1892 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
H A Drockchip_vop2_reg.c802 .htotal_pw = VOP_REG(RK3568_VP0_DSP_HTOTAL_HS_END, 0xffffffff, 0),
878 .htotal_pw = VOP_REG(RK3568_VP1_DSP_HTOTAL_HS_END, 0xffffffff, 0),
994 .htotal_pw = VOP_REG(RK3568_VP0_DSP_HTOTAL_HS_END, 0xffffffff, 0),
1076 .htotal_pw = VOP_REG(RK3568_VP0_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
1163 .htotal_pw = VOP_REG(RK3568_VP1_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
1219 .htotal_pw = VOP_REG(RK3568_VP2_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
1316 .htotal_pw = VOP_REG(RK3568_VP0_DSP_HTOTAL_HS_END, 0xffffffff, 0),
1417 .htotal_pw = VOP_REG(RK3568_VP1_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
1514 .htotal_pw = VOP_REG(RK3568_VP2_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
1581 .htotal_pw = VOP_REG(RK3588_VP3_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
H A Drockchip_drm_vop.h254 struct vop_reg htotal_pw; member
792 struct vop_reg htotal_pw; member
H A Drockchip_drm_vop.c3232 if (htotal_sync != VOP_CTRL_GET(vop, htotal_pw) || in vop_crtc_mode_update()
3392 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); in vop_crtc_atomic_enable()
H A Drockchip_drm_vop2.c4310 u32 htotal = (VOP_MODULE_GET(vop2, vp, htotal_pw) >> 16) & 0xffff; in vop2_crtc_atomic_enter_psr()
6995 if (htotal_sync != VOP_MODULE_GET(vop2, vp, htotal_pw) || in vop2_crtc_mode_update()
8008 VOP_MODULE_SET(vop2, vp, htotal_pw, (htotal << 16) | hsync_len); in vop2_crtc_atomic_enable()
9923 u16 htotal = VOP_MODULE_GET(vop2, vp, htotal_pw) >> 16; in vop2_sleep_scan_line_time()