Searched refs:davinci_emif_regs (Results 1 – 7 of 7) sorted by relevance
170 ecc = __raw_readl(&(davinci_emif_regs->nandfecc[ in nand_davinci_readecc()183 val = __raw_readl(&davinci_emif_regs->nandfcr); in nand_davinci_enable_hwecc()186 __raw_writel(val, &davinci_emif_regs->nandfcr); in nand_davinci_enable_hwecc()485 val = __raw_readl(&davinci_emif_regs->nandfcr); in nand_davinci_4bit_enable_hwecc()490 __raw_writel(val, &davinci_emif_regs->nandfcr); in nand_davinci_4bit_enable_hwecc()493 val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]); in nand_davinci_4bit_enable_hwecc()505 ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) & in nand_davinci_4bit_readecc()591 &davinci_emif_regs->nand4biteccload); in nand_davinci_4bit_correct_data()595 &davinci_emif_regs->nand4biteccload); in nand_davinci_4bit_correct_data()599 &davinci_emif_regs->nand4biteccload); in nand_davinci_4bit_correct_data()[all …]
31 struct davinci_emif_regs { struct74 #define davinci_emif_regs \ argument75 ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE)
364 writel(CONFIG_SYS_DM36x_AWCCR, &davinci_emif_regs->awccr); in dm365_emif_init()365 writel(CONFIG_SYS_DM36x_AB1CR, &davinci_emif_regs->ab1cr); in dm365_emif_init()367 setbits_le32(&davinci_emif_regs->nandfcr, DAVINCI_NANDFCR_CS2NAND); in dm365_emif_init()369 writel(CONFIG_SYS_DM36x_AB2CR, &davinci_emif_regs->ab2cr); in dm365_emif_init()
281 writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr); in arch_cpu_init()284 writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr); in arch_cpu_init()
222 &davinci_emif_regs->ab1cr); /* CS2 */ in board_early_init_f()
208 &davinci_emif_regs->ab2cr); /* CS3 */ in board_init()
342 &davinci_emif_regs->ab2cr); /* CS3 */ in board_init()