1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * NAND Flash Driver 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2006-2014 Texas Instruments. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Based on Linux DaVinci NAND driver by TI. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _DAVINCI_NAND_H_ 10*4882a593Smuzhiyun #define _DAVINCI_NAND_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/mtd/rawnand.h> 13*4882a593Smuzhiyun #include <asm/arch/hardware.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define NAND_READ_START 0x00 16*4882a593Smuzhiyun #define NAND_READ_END 0x30 17*4882a593Smuzhiyun #define NAND_STATUS 0x70 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define MASK_CLE 0x10 20*4882a593Smuzhiyun #define MASK_ALE 0x08 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #ifdef CONFIG_SYS_NAND_MASK_CLE 23*4882a593Smuzhiyun #undef MASK_CLE 24*4882a593Smuzhiyun #define MASK_CLE CONFIG_SYS_NAND_MASK_CLE 25*4882a593Smuzhiyun #endif 26*4882a593Smuzhiyun #ifdef CONFIG_SYS_NAND_MASK_ALE 27*4882a593Smuzhiyun #undef MASK_ALE 28*4882a593Smuzhiyun #define MASK_ALE CONFIG_SYS_NAND_MASK_ALE 29*4882a593Smuzhiyun #endif 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun struct davinci_emif_regs { 32*4882a593Smuzhiyun uint32_t ercsr; 33*4882a593Smuzhiyun uint32_t awccr; 34*4882a593Smuzhiyun uint32_t sdbcr; 35*4882a593Smuzhiyun uint32_t sdrcr; 36*4882a593Smuzhiyun union { 37*4882a593Smuzhiyun uint32_t abncr[4]; 38*4882a593Smuzhiyun struct { 39*4882a593Smuzhiyun uint32_t ab1cr; 40*4882a593Smuzhiyun uint32_t ab2cr; 41*4882a593Smuzhiyun uint32_t ab3cr; 42*4882a593Smuzhiyun uint32_t ab4cr; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun uint32_t sdtimr; 46*4882a593Smuzhiyun uint32_t ddrsr; 47*4882a593Smuzhiyun uint32_t ddrphycr; 48*4882a593Smuzhiyun uint32_t ddrphysr; 49*4882a593Smuzhiyun uint32_t totar; 50*4882a593Smuzhiyun uint32_t totactr; 51*4882a593Smuzhiyun uint32_t ddrphyid_rev; 52*4882a593Smuzhiyun uint32_t sdsretr; 53*4882a593Smuzhiyun uint32_t eirr; 54*4882a593Smuzhiyun uint32_t eimr; 55*4882a593Smuzhiyun uint32_t eimsr; 56*4882a593Smuzhiyun uint32_t eimcr; 57*4882a593Smuzhiyun uint32_t ioctrlr; 58*4882a593Smuzhiyun uint32_t iostatr; 59*4882a593Smuzhiyun uint32_t rsvd0; 60*4882a593Smuzhiyun uint32_t one_nand_cr; 61*4882a593Smuzhiyun uint32_t nandfcr; 62*4882a593Smuzhiyun uint32_t nandfsr; 63*4882a593Smuzhiyun uint32_t rsvd1[2]; 64*4882a593Smuzhiyun uint32_t nandfecc[4]; 65*4882a593Smuzhiyun uint32_t rsvd2[15]; 66*4882a593Smuzhiyun uint32_t nand4biteccload; 67*4882a593Smuzhiyun uint32_t nand4bitecc[4]; 68*4882a593Smuzhiyun uint32_t nanderradd1; 69*4882a593Smuzhiyun uint32_t nanderradd2; 70*4882a593Smuzhiyun uint32_t nanderrval1; 71*4882a593Smuzhiyun uint32_t nanderrval2; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define davinci_emif_regs \ 75*4882a593Smuzhiyun ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << ((n) - 2)) 78*4882a593Smuzhiyun #define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4) 79*4882a593Smuzhiyun #define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) (((n) - 2) << 4) 80*4882a593Smuzhiyun #define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + ((n) - 2))) 81*4882a593Smuzhiyun #define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) 82*4882a593Smuzhiyun #define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) 83*4882a593Smuzhiyun #define DAVINCI_NANDFCR_CS2NAND (1 << 0) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* Chip Select setup */ 86*4882a593Smuzhiyun #define DAVINCI_ABCR_STROBE_SELECT (1 << 31) 87*4882a593Smuzhiyun #define DAVINCI_ABCR_EXT_WAIT (1 << 30) 88*4882a593Smuzhiyun #define DAVINCI_ABCR_WSETUP(n) (n << 26) 89*4882a593Smuzhiyun #define DAVINCI_ABCR_WSTROBE(n) (n << 20) 90*4882a593Smuzhiyun #define DAVINCI_ABCR_WHOLD(n) (n << 17) 91*4882a593Smuzhiyun #define DAVINCI_ABCR_RSETUP(n) (n << 13) 92*4882a593Smuzhiyun #define DAVINCI_ABCR_RSTROBE(n) (n << 7) 93*4882a593Smuzhiyun #define DAVINCI_ABCR_RHOLD(n) (n << 4) 94*4882a593Smuzhiyun #define DAVINCI_ABCR_TA(n) (n << 2) 95*4882a593Smuzhiyun #define DAVINCI_ABCR_ASIZE_16BIT 1 96*4882a593Smuzhiyun #define DAVINCI_ABCR_ASIZE_8BIT 0 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun void davinci_nand_init(struct nand_chip *nand); 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #endif 101