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Searched refs:_refdiv (Results 1 – 7 of 7) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/clk/rockchip/regmap/
H A Dclk-regmap-pll.c111 u8 _dsmpd = 1, _postdiv1 = 0, _postdiv2 = 0, _refdiv = 0; in clk_pll_round_rate() local
161 for (_refdiv = min_refdiv; _refdiv <= max_refdiv; _refdiv++) { in clk_pll_round_rate()
164 if (fin % _refdiv) in clk_pll_round_rate()
167 tmp = (u64)fout * _refdiv; in clk_pll_round_rate()
174 do_div(tmp, _refdiv); in clk_pll_round_rate()
181 tmp = (u64)frac_rate * _refdiv; in clk_pll_round_rate()
201 do_div(foutvco, _refdiv); in clk_pll_round_rate()
206 do_div(frac_rate, _refdiv); in clk_pll_round_rate()
215 *refdiv = _refdiv; in clk_pll_round_rate()
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dclock.h67 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ argument
73 .refdiv = _refdiv, \
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk3036.c49 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
50 .refdiv = _refdiv,\
51 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
53 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
54 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
H A Dclk_rv1108.c31 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
32 .refdiv = _refdiv,\
33 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
35 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
36 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
H A Dclk_rk3399.c48 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
49 .refdiv = _refdiv,\
50 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
H A Dclk_px30.c32 #define PX30_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ argument
38 .refdiv = _refdiv, \
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk.h456 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ argument
462 .refdiv = _refdiv, \