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Searched refs:_postdiv2 (Results 1 – 7 of 7) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/clk/rockchip/regmap/
H A Dclk-regmap-pll.c111 u8 _dsmpd = 1, _postdiv1 = 0, _postdiv2 = 0, _refdiv = 0; in clk_pll_round_rate() local
142 for (_postdiv2 = 1; _postdiv2 < 8; _postdiv2++) { in clk_pll_round_rate()
143 if (postdiv % _postdiv2) in clk_pll_round_rate()
146 _postdiv1 = postdiv / _postdiv2; in clk_pll_round_rate()
152 if (_postdiv2 > 7) in clk_pll_round_rate()
155 fout *= _postdiv1 * _postdiv2; in clk_pll_round_rate()
158 _postdiv2 = 1; in clk_pll_round_rate()
212 do_div(foutpostdiv, _postdiv2); in clk_pll_round_rate()
221 *postdiv2 = _postdiv2; in clk_pll_round_rate()
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dclock.h68 _postdiv2, _dsmpd, _frac) \ argument
74 .postdiv2 = _postdiv2, \
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk3036.c49 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
51 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
52 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
53 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
54 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
H A Dclk_rv1108.c31 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
33 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
34 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
35 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
36 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
H A Dclk_rk3399.c48 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
50 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
51 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2, .freq = hz};
H A Dclk_px30.c33 _postdiv2, _dsmpd, _frac) \ argument
39 .postdiv2 = _postdiv2, \
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk.h457 _postdiv2, _dsmpd, _frac) \ argument
463 .postdiv2 = _postdiv2, \