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Searched refs:R_0x1ce8 (Results 1 – 24 of 24) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8188eu/hal/phydm/
H A Dphydm_adc_sampling.c94 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 1); /*@AND 1 val*/ in phydm_la_pre_run()
114 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 0); /*@AND 1 val*/ in phydm_la_pre_run()
233 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), 0); /*@AND 1 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
235 odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, 0); in phydm_la_bb_adv_trig_setting_jgr3()
236 odm_set_bb_reg(dm, R_0x1ce8, BIT(15), 0); /*@AND 2 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
238 odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, 0); in phydm_la_bb_adv_trig_setting_jgr3()
239 odm_set_bb_reg(dm, R_0x1ce8, BIT(25), 0); /*@AND 3 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
242 odm_set_bb_reg(dm, R_0x1ce8, BIT(26), 0); /*@AND 4 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
250 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), adv->la_and1_inv); in phydm_la_bb_adv_trig_setting_jgr3()
252 odm_set_bb_reg(dm, R_0x1ce8, 0x1f, adv->la_and1_val); in phydm_la_bb_adv_trig_setting_jgr3()
[all …]
H A Dphydm_regtable.h213 #define R_0x1ce8 0x1ce8 macro
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8189fs/hal/phydm/
H A Dphydm_adc_sampling.c94 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 1); /*@AND 1 val*/ in phydm_la_pre_run()
114 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 0); /*@AND 1 val*/ in phydm_la_pre_run()
233 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), 0); /*@AND 1 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
235 odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, 0); in phydm_la_bb_adv_trig_setting_jgr3()
236 odm_set_bb_reg(dm, R_0x1ce8, BIT(15), 0); /*@AND 2 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
238 odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, 0); in phydm_la_bb_adv_trig_setting_jgr3()
239 odm_set_bb_reg(dm, R_0x1ce8, BIT(25), 0); /*@AND 3 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
242 odm_set_bb_reg(dm, R_0x1ce8, BIT(26), 0); /*@AND 4 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
250 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), adv->la_and1_inv); in phydm_la_bb_adv_trig_setting_jgr3()
252 odm_set_bb_reg(dm, R_0x1ce8, 0x1f, adv->la_and1_val); in phydm_la_bb_adv_trig_setting_jgr3()
[all …]
H A Dphydm_regtable.h213 #define R_0x1ce8 0x1ce8 macro
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8188fu/hal/phydm/
H A Dphydm_adc_sampling.c94 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 1); /*@AND 1 val*/ in phydm_la_pre_run()
114 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 0); /*@AND 1 val*/ in phydm_la_pre_run()
233 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), 0); /*@AND 1 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
235 odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, 0); in phydm_la_bb_adv_trig_setting_jgr3()
236 odm_set_bb_reg(dm, R_0x1ce8, BIT(15), 0); /*@AND 2 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
238 odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, 0); in phydm_la_bb_adv_trig_setting_jgr3()
239 odm_set_bb_reg(dm, R_0x1ce8, BIT(25), 0); /*@AND 3 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
242 odm_set_bb_reg(dm, R_0x1ce8, BIT(26), 0); /*@AND 4 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
250 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), adv->la_and1_inv); in phydm_la_bb_adv_trig_setting_jgr3()
252 odm_set_bb_reg(dm, R_0x1ce8, 0x1f, adv->la_and1_val); in phydm_la_bb_adv_trig_setting_jgr3()
[all …]
H A Dphydm_regtable.h213 #define R_0x1ce8 0x1ce8 macro
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723cs/hal/phydm/
H A Dphydm_adc_sampling.c93 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 1); /*@AND 1 val*/ in phydm_la_pre_run()
113 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 0); /*@AND 1 val*/ in phydm_la_pre_run()
233 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), 0); /*@AND 1 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
235 odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, 0); in phydm_la_bb_adv_trig_setting_jgr3()
236 odm_set_bb_reg(dm, R_0x1ce8, BIT(15), 0); /*@AND 2 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
238 odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, 0); in phydm_la_bb_adv_trig_setting_jgr3()
239 odm_set_bb_reg(dm, R_0x1ce8, BIT(25), 0); /*@AND 3 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
242 odm_set_bb_reg(dm, R_0x1ce8, BIT(26), 0); /*@AND 4 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
250 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), adv->la_and1_inv); in phydm_la_bb_adv_trig_setting_jgr3()
252 odm_set_bb_reg(dm, R_0x1ce8, 0x1f, adv->la_and1_val); in phydm_la_bb_adv_trig_setting_jgr3()
[all …]
H A Dphydm_regtable.h260 #define R_0x1ce8 0x1ce8 macro
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8822bs/hal/phydm/
H A Dphydm_adc_sampling.c93 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 1); /*@AND 1 val*/ in phydm_la_pre_run()
113 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 0); /*@AND 1 val*/ in phydm_la_pre_run()
219 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), 0); /*@AND 1 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
221 odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, 0); in phydm_la_bb_adv_trig_setting_jgr3()
222 odm_set_bb_reg(dm, R_0x1ce8, BIT(15), 0); /*@AND 2 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
224 odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, 0); in phydm_la_bb_adv_trig_setting_jgr3()
225 odm_set_bb_reg(dm, R_0x1ce8, BIT(25), 0); /*@AND 3 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
228 odm_set_bb_reg(dm, R_0x1ce8, BIT(26), 0); /*@AND 4 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
236 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), adv->la_and1_inv); in phydm_la_bb_adv_trig_setting_jgr3()
238 odm_set_bb_reg(dm, R_0x1ce8, 0x1f, adv->la_and1_val); in phydm_la_bb_adv_trig_setting_jgr3()
[all …]
H A Dphydm_regtable.h215 #define R_0x1ce8 0x1ce8 macro
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8821cs/hal/phydm/
H A Dphydm_adc_sampling.c94 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 1); /*@AND 1 val*/ in phydm_la_pre_run()
114 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 0); /*@AND 1 val*/ in phydm_la_pre_run()
234 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), 0); /*@AND 1 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
236 odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, 0); in phydm_la_bb_adv_trig_setting_jgr3()
237 odm_set_bb_reg(dm, R_0x1ce8, BIT(15), 0); /*@AND 2 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
239 odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, 0); in phydm_la_bb_adv_trig_setting_jgr3()
240 odm_set_bb_reg(dm, R_0x1ce8, BIT(25), 0); /*@AND 3 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
243 odm_set_bb_reg(dm, R_0x1ce8, BIT(26), 0); /*@AND 4 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
251 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), adv->la_and1_inv); in phydm_la_bb_adv_trig_setting_jgr3()
253 odm_set_bb_reg(dm, R_0x1ce8, 0x1f, adv->la_and1_val); in phydm_la_bb_adv_trig_setting_jgr3()
[all …]
H A Dphydm_regtable.h260 #define R_0x1ce8 0x1ce8 macro
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8189fs/hal/phydm/
H A Dphydm_adc_sampling.c93 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 1); /*@AND 1 val*/ in phydm_la_pre_run()
113 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 0); /*@AND 1 val*/ in phydm_la_pre_run()
219 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), 0); /*@AND 1 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
221 odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, 0); in phydm_la_bb_adv_trig_setting_jgr3()
222 odm_set_bb_reg(dm, R_0x1ce8, BIT(15), 0); /*@AND 2 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
224 odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, 0); in phydm_la_bb_adv_trig_setting_jgr3()
225 odm_set_bb_reg(dm, R_0x1ce8, BIT(25), 0); /*@AND 3 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
228 odm_set_bb_reg(dm, R_0x1ce8, BIT(26), 0); /*@AND 4 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
236 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), adv->la_and1_inv); in phydm_la_bb_adv_trig_setting_jgr3()
238 odm_set_bb_reg(dm, R_0x1ce8, 0x1f, adv->la_and1_val); in phydm_la_bb_adv_trig_setting_jgr3()
[all …]
H A Dphydm_regtable.h244 #define R_0x1ce8 0x1ce8 macro
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723ds/hal/phydm/
H A Dphydm_adc_sampling.c94 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 1); /*@AND 1 val*/ in phydm_la_pre_run()
114 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 0); /*@AND 1 val*/ in phydm_la_pre_run()
220 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), 0); /*@AND 1 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
222 odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, 0); in phydm_la_bb_adv_trig_setting_jgr3()
223 odm_set_bb_reg(dm, R_0x1ce8, BIT(15), 0); /*@AND 2 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
225 odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, 0); in phydm_la_bb_adv_trig_setting_jgr3()
226 odm_set_bb_reg(dm, R_0x1ce8, BIT(25), 0); /*@AND 3 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
229 odm_set_bb_reg(dm, R_0x1ce8, BIT(26), 0); /*@AND 4 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
237 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), adv->la_and1_inv); in phydm_la_bb_adv_trig_setting_jgr3()
239 odm_set_bb_reg(dm, R_0x1ce8, 0x1f, adv->la_and1_val); in phydm_la_bb_adv_trig_setting_jgr3()
[all …]
H A Dphydm_regtable.h220 #define R_0x1ce8 0x1ce8 macro
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8188fu/hal/phydm/
H A Dphydm_adc_sampling.c93 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 1); /*@AND 1 val*/ in phydm_la_pre_run()
113 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 0); /*@AND 1 val*/ in phydm_la_pre_run()
219 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), 0); /*@AND 1 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
221 odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, 0); in phydm_la_bb_adv_trig_setting_jgr3()
222 odm_set_bb_reg(dm, R_0x1ce8, BIT(15), 0); /*@AND 2 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
224 odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, 0); in phydm_la_bb_adv_trig_setting_jgr3()
225 odm_set_bb_reg(dm, R_0x1ce8, BIT(25), 0); /*@AND 3 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
228 odm_set_bb_reg(dm, R_0x1ce8, BIT(26), 0); /*@AND 4 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
236 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), adv->la_and1_inv); in phydm_la_bb_adv_trig_setting_jgr3()
238 odm_set_bb_reg(dm, R_0x1ce8, 0x1f, adv->la_and1_val); in phydm_la_bb_adv_trig_setting_jgr3()
[all …]
H A Dphydm_regtable.h244 #define R_0x1ce8 0x1ce8 macro
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8821cs/hal/phydm/
H A Dphydm_adc_sampling.c93 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 1); /*@AND 1 val*/ in phydm_la_pre_run()
113 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 0); /*@AND 1 val*/ in phydm_la_pre_run()
300 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), 0); /*@AND 1 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
302 odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, 0); in phydm_la_bb_adv_trig_setting_jgr3()
303 odm_set_bb_reg(dm, R_0x1ce8, BIT(15), 0); /*@AND 2 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
305 odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, 0); in phydm_la_bb_adv_trig_setting_jgr3()
306 odm_set_bb_reg(dm, R_0x1ce8, BIT(25), 0); /*@AND 3 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
309 odm_set_bb_reg(dm, R_0x1ce8, BIT(26), 0); /*@AND 4 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
317 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), adv->la_and1_inv); in phydm_la_bb_adv_trig_setting_jgr3()
319 odm_set_bb_reg(dm, R_0x1ce8, 0x1f, adv->la_and1_val); in phydm_la_bb_adv_trig_setting_jgr3()
[all …]
H A Dphydm_regtable.h270 #define R_0x1ce8 0x1ce8 macro
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8822cs/hal/phydm/
H A Dphydm_adc_sampling.c93 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 1); /*@AND 1 val*/ in phydm_la_pre_run()
113 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 0); /*@AND 1 val*/ in phydm_la_pre_run()
300 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), 0); /*@AND 1 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
302 odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, 0); in phydm_la_bb_adv_trig_setting_jgr3()
303 odm_set_bb_reg(dm, R_0x1ce8, BIT(15), 0); /*@AND 2 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
305 odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, 0); in phydm_la_bb_adv_trig_setting_jgr3()
306 odm_set_bb_reg(dm, R_0x1ce8, BIT(25), 0); /*@AND 3 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
309 odm_set_bb_reg(dm, R_0x1ce8, BIT(26), 0); /*@AND 4 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
317 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), adv->la_and1_inv); in phydm_la_bb_adv_trig_setting_jgr3()
319 odm_set_bb_reg(dm, R_0x1ce8, 0x1f, adv->la_and1_val); in phydm_la_bb_adv_trig_setting_jgr3()
[all …]
H A Dphydm_regtable.h269 #define R_0x1ce8 0x1ce8 macro
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8723ds/hal/phydm/
H A Dphydm_adc_sampling.c93 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 1); /*@AND 1 val*/ in phydm_la_pre_run()
113 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 0); /*@AND 1 val*/ in phydm_la_pre_run()
300 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), 0); /*@AND 1 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
302 odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, 0); in phydm_la_bb_adv_trig_setting_jgr3()
303 odm_set_bb_reg(dm, R_0x1ce8, BIT(15), 0); /*@AND 2 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
305 odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, 0); in phydm_la_bb_adv_trig_setting_jgr3()
306 odm_set_bb_reg(dm, R_0x1ce8, BIT(25), 0); /*@AND 3 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
309 odm_set_bb_reg(dm, R_0x1ce8, BIT(26), 0); /*@AND 4 inv*/ in phydm_la_bb_adv_trig_setting_jgr3()
317 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), adv->la_and1_inv); in phydm_la_bb_adv_trig_setting_jgr3()
319 odm_set_bb_reg(dm, R_0x1ce8, 0x1f, adv->la_and1_val); in phydm_la_bb_adv_trig_setting_jgr3()
[all …]
H A Dphydm_regtable.h268 #define R_0x1ce8 0x1ce8 macro