1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #include "mp_precomp.h"
27 #include "phydm_precomp.h"
28
29 #if (PHYDM_LA_MODE_SUPPORT)
30
31 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
32 #if (RTL8197F_SUPPORT || RTL8822B_SUPPORT || RTL8192F_SUPPORT)
33 #include "rtl8197f/Hal8197FPhyReg.h"
34 #include "WlanHAL/HalMac88XX/halmac_reg2.h"
35 #else
36 #include "WlanHAL/HalHeader/HalComReg.h"
37 #endif
38 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
39 #if WPP_SOFTWARE_TRACE
40 #include "phydm_adc_sampling.tmh"
41 #endif
42 #endif
43
44 #if RTL8814B_SUPPORT
phydm_la_finish_addr_recover_8814B(void * dm_void,u32 * finish_addr)45 boolean phydm_la_finish_addr_recover_8814B(void *dm_void, u32 *finish_addr)
46 {
47 struct dm_struct *dm = (struct dm_struct *)dm_void;
48 struct rt_adcsmp *smp = &dm->adcsmp;
49 boolean recover_success;
50
51 if (dm->support_ic_type != ODM_RTL8814B)
52 return false;
53
54 if (smp->la_buff_mode == ADCSMP_BUFF_HALF) {
55 if (*finish_addr < 0x4000) /*0~0x4000*/
56 *finish_addr += 0x8000;
57
58 recover_success = true;
59 } else {
60 if (*finish_addr >= 0x4000 && *finish_addr < 0x8000)
61 recover_success = true;
62 else
63 recover_success = false;
64 }
65 pr_debug("[8814B] recover_success=(%d)\n", recover_success);
66
67 return recover_success;
68 }
69 #endif
70
71 #if RTL8198F_SUPPORT
phydm_la_pre_run(void * dm_void)72 void phydm_la_pre_run(void *dm_void)
73 {
74 struct dm_struct *dm = (struct dm_struct *)dm_void;
75 struct rt_adcsmp *smp = &dm->adcsmp;
76 struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
77 u8 i = 0;
78 u8 tmp = 0;
79 u8 target_polling_bit = BIT(1);
80
81 if (!(dm->support_ic_type & ODM_RTL8198F))
82 return;
83
84 if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG)
85 return;
86
87 /*pre run */
88 /*force to bb trigger*/
89 odm_set_mac_reg(dm, R_0x7c0, BIT(3), 0);
90 /*dma_trig_and(AND1) output 1*/
91 odm_set_bb_reg(dm, R_0x1ce4, 0xf0000000, 0x0);
92 /*r_dma_trigger_AND1_inv = 1*/
93 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 1); /*@AND 1 val*/
94 /* polling bit for BB ADC mode */
95 odm_set_mac_reg(dm, R_0x7c0, BIT(1), 1);
96
97 pr_debug("buf[end:start]=(0x%x~0x%x)\n", buf->end_pos, buf->start_pos);
98
99 do {
100 tmp = odm_read_1byte(dm, R_0x7c0);
101 if ((tmp & target_polling_bit) == false) {
102 pr_debug("LA pre-run fail.\n");
103 phydm_la_stop(dm);
104 phydm_release_bb_dbg_port(dm);
105 } else {
106 ODM_delay_ms(100);
107 pr_debug("LA pre-run while_cnt = %d.\n", i);
108 i++;
109 }
110 } while (i < 3);
111
112 /*r_dma_trigger_AND1_inv = 0*/
113 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 0); /*@AND 1 val*/
114
115 if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG)
116 odm_set_mac_reg(dm, R_0x7c0, BIT(3), 1);
117 }
118 #endif
119
120 #if (RTL8821C_SUPPORT || RTL8195B_SUPPORT)
121 void
phydm_la_clk_en(void * dm_void,boolean enable)122 phydm_la_clk_en(void *dm_void, boolean enable)
123 {
124 struct dm_struct *dm = (struct dm_struct *)dm_void;
125 u8 val = (enable) ? 1 : 0;
126
127 if (!(dm->support_ic_type & (ODM_RTL8195B | ODM_RTL8821C)))
128 return;
129
130 if (dm->support_ic_type == ODM_RTL8821C &&
131 dm->cut_version == ODM_CUT_A)
132 return;
133
134 odm_set_bb_reg(dm, R_0x95c, BIT(23), val);
135 }
136 #endif
137
138 #if (RTL8197F_SUPPORT)
139 void
phydm_la_stop_dma_8197f(void * dm_void,enum phydm_backup_type opt)140 phydm_la_stop_dma_8197f(void *dm_void, enum phydm_backup_type opt)
141 {
142 struct dm_struct *dm = (struct dm_struct *)dm_void;
143 struct rt_adcsmp *smp = &dm->adcsmp;
144
145 if (dm->support_ic_type != ODM_RTL8197F)
146 return;
147
148 if (opt == PHYDM_BACKUP) {
149 /*Stop DMA*/
150 smp->backup_dma = odm_get_mac_reg(dm, R_0x300, 0xffff);
151 odm_set_mac_reg(dm, R_0x300, 0x7fff, 0x7fff);
152 } else { /*restore*/
153 /*Resume DMA*/
154 odm_set_mac_reg(dm, R_0x300, 0x7fff, smp->backup_dma);
155 }
156 }
157 #endif
158
159 #ifdef PHYDM_COMPILE_LA_STORE_IN_IMEM
160 void
phydm_la_mv_data_2_tx_buffer(void * dm_void)161 phydm_la_mv_data_2_tx_buffer(void *dm_void)
162 {
163 struct dm_struct *dm = (struct dm_struct *)dm_void;
164 struct rt_adcsmp *smp = &dm->adcsmp;
165 struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
166
167 if (!(dm->support_ic_type & PHYDM_LA_STORE_IN_IMEM_IC))
168 return;
169
170 pr_debug("GetTxPktBuf from iMEM\n");
171 odm_set_mac_reg(dm, R_0x7c0, BIT(0), 0x0); /*Disable LA mode HW block*/
172
173 /* 98F LA memory loccation is separate from normal
174 * driver use, DMA is no longer required to stop
175 */
176 #if (RTL8197F_SUPPORT)
177 phydm_la_stop_dma_8197f(dm, PHYDM_BACKUP);
178 #endif
179
180 /* @move LA mode content from IMEM to TxPktBuffer
181 * Source : OCPBASE_IMEM 0x00000000
182 * Destination : OCPBASE_TXBUF 0x18780000
183 * Length : 64K
184 */
185 GET_HAL_INTERFACE(dm->priv)->init_ddma_handler(dm->priv,
186 OCPBASE_IMEM,
187 OCPBASE_TXBUF
188 + buf->start_pos,
189 0x10000);
190 }
191 #endif
192
193 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
194
phydm_la_bb_adv_reset_jgr3(void * dm_void)195 void phydm_la_bb_adv_reset_jgr3(void *dm_void)
196 {
197 struct dm_struct *dm = (struct dm_struct *)dm_void;
198 struct rt_adcsmp *smp = &dm->adcsmp;
199 struct la_adv_trig *adv = &smp->adv_trig_table;
200
201 odm_memory_set(dm, adv, 0, sizeof(struct la_adv_trig));
202
203 }
204
phydm_la_bb_adv_trig_setting_jgr3(void * dm_void)205 void phydm_la_bb_adv_trig_setting_jgr3(void *dm_void)
206 {
207 struct dm_struct *dm = (struct dm_struct *)dm_void;
208 struct rt_adcsmp *smp = &dm->adcsmp;
209 struct la_adv_trig *adv = &smp->adv_trig_table;
210
211 pr_debug(" *ADV BB-trig = %d\n", adv->la_adv_bbtrigger_en);
212
213 if (!adv->la_adv_bbtrigger_en) { /*normal LA mode & back to default*/
214 /*@AND0*/
215 odm_set_bb_reg(dm, R_0x1ce4, BIT(27), 0);
216
217 /*@AND1*/
218 odm_set_bb_reg(dm, R_0x1ce4, MASKH4BITS, 0);
219 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), 0); /*@AND 1 inv*/
220 /*@AND2*/
221 odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, 0);
222 odm_set_bb_reg(dm, R_0x1ce8, BIT(15), 0); /*@AND 2 inv*/
223 /*@AND3*/
224 odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, 0);
225 odm_set_bb_reg(dm, R_0x1ce8, BIT(25), 0); /*@AND 3 inv*/
226 /*@AND4*/
227 odm_set_bb_reg(dm, R_0x1cf0, MASKDWORD, 0); /*@AND 4 mask en*/
228 odm_set_bb_reg(dm, R_0x1ce8, BIT(26), 0); /*@AND 4 inv*/
229 } else {
230 /*@AND0 */
231 /*path 1 default: enable ori. BB trigger*/
232 odm_set_bb_reg(dm, R_0x1ce4, BIT(27),
233 (adv->la_ori_bb_dis ? 1 : 0));
234
235 /* @AND1 */
236 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), adv->la_and1_inv);
237 odm_set_bb_reg(dm, R_0x1ce4, MASKH4BITS, adv->la_and1_sel);
238 odm_set_bb_reg(dm, R_0x1ce8, 0x1f, adv->la_and1_val);
239
240 /*@AND2 */
241 odm_set_bb_reg(dm, R_0x1ce8, BIT(15), adv->la_and2_inv);
242 odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, adv->la_and2_sel);
243 odm_set_bb_reg(dm, R_0x1ce8, 0x7c00, adv->la_and2_val);
244
245 /*@AND3 */
246 odm_set_bb_reg(dm, R_0x1ce8, BIT(25), adv->la_and3_inv);
247 odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, adv->la_and3_sel);
248 odm_set_bb_reg(dm, R_0x1ce8, 0x1f00000, adv->la_and3_val);
249
250 /*@AND4 */
251 odm_set_bb_reg(dm, R_0x1ce8, BIT(26), adv->la_and4_inv);
252 odm_set_bb_reg(dm, R_0x1cf0, MASKDWORD, adv->la_and4_mask);
253 odm_set_bb_reg(dm, R_0x1cec, MASKDWORD, adv->la_and4_bitmap);
254 }
255 }
256
phydm_la_bb_adv_cmd_show_jgr3(void * dm_void,u32 * _used,char * output,u32 * _out_len)257 void phydm_la_bb_adv_cmd_show_jgr3(void *dm_void, u32 *_used,
258 char *output, u32 *_out_len)
259 {
260 struct dm_struct *dm = (struct dm_struct *)dm_void;
261 struct rt_adcsmp *smp = &dm->adcsmp;
262 struct la_adv_trig *adv = &smp->adv_trig_table;
263
264 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
265 " *And0 Disable=%d\n", adv->la_ori_bb_dis);
266 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
267 " *And1{sel,val,inv}={0x%x,0x%x,%d}\n *And2{sel,val,inv}={0x%x,0x%x,%d}\n *And3{sel,val,inv}={0x%x,0x%x,%d}\n",
268 adv->la_and1_sel, adv->la_and1_val, adv->la_and1_inv,
269 adv->la_and2_sel, adv->la_and2_val, adv->la_and2_inv,
270 adv->la_and3_sel, adv->la_and3_val, adv->la_and3_inv);
271 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
272 " *And4{mask,bitmap,inv}={0x%x,0x%x,%d}\n",
273 adv->la_and4_mask, adv->la_and4_bitmap, adv->la_and4_inv);
274 }
275
phydm_la_bb_adv_cmd_jgr3(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)276 void phydm_la_bb_adv_cmd_jgr3(void *dm_void, char input[][16], u32 *_used,
277 char *output, u32 *_out_len)
278 {
279 struct dm_struct *dm = (struct dm_struct *)dm_void;
280 struct rt_adcsmp *smp = &dm->adcsmp;
281 struct la_adv_trig *adv = &smp->adv_trig_table;
282 u32 var1[10] = {0};
283 u32 adv_trig_en;
284
285 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
286 return;
287
288 if ((strcmp(input[2], "show") == 0)) {
289 phydm_la_bb_adv_cmd_show_jgr3(dm, _used, output, _out_len);
290 return;
291 }
292
293 PHYDM_SSCANF(input[2], DCMD_HEX, &var1[0]);
294 PHYDM_SSCANF(input[3], DCMD_HEX, &var1[1]);
295 PHYDM_SSCANF(input[4], DCMD_HEX, &var1[2]);
296 PHYDM_SSCANF(input[5], DCMD_HEX, &var1[3]);
297 PHYDM_SSCANF(input[6], DCMD_HEX, &var1[4]);
298
299 adv_trig_en = var1[0];
300
301 if (adv_trig_en != 1) {
302 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
303 "Back to Ori-BB-trig\n");
304 phydm_la_bb_adv_reset_jgr3(dm);
305 return;
306 }
307
308 adv->la_adv_bbtrigger_en = true;
309
310 if (var1[1] == 0) {
311 adv->la_ori_bb_dis = (boolean)var1[2];
312 } else if (var1[1] == 1) {
313 adv->la_and1_sel = (u8)var1[2];
314 adv->la_and1_val = (u8)var1[3];
315 adv->la_and1_inv = (boolean)var1[4];
316 } else if (var1[1] == 2) {
317 adv->la_and2_sel = (u8)var1[2];
318 adv->la_and2_val = (u8)var1[3];
319 adv->la_and2_inv = (boolean)var1[4];
320 } else if (var1[1] == 3) {
321 adv->la_and3_sel = (u8)var1[2];
322 adv->la_and3_val = (u8)var1[3];
323 adv->la_and2_inv = (boolean)var1[4];
324 } else if (var1[1] == 4) {
325 adv->la_and4_mask = var1[2];
326 adv->la_and4_bitmap = var1[3];
327 adv->la_and4_inv = (boolean)var1[4];
328 }
329
330 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
331 "[Adv_trig_en=%d]\n\n", adv_trig_en);
332
333 phydm_la_bb_adv_cmd_show_jgr3(dm, _used, output, _out_len);
334 }
335
phydm_la_cmd_fast_jgr3(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)336 void phydm_la_cmd_fast_jgr3(void *dm_void, char input[][16], u32 *_used,
337 char *output, u32 *_out_len)
338 {
339 struct dm_struct *dm = (struct dm_struct *)dm_void;
340 struct rt_adcsmp *smp = &dm->adcsmp;
341 struct la_adv_trig *adv = &smp->adv_trig_table;
342 enum auto_detection_state ad_mode;
343 const u8 ofdm_codeword[8] = {0xb, 0xf, 0xa, 0xe, 0x9, 0xd, 0x8, 0xc};
344 u32 codeword;
345 u8 rate_idx;
346 u32 trig_time_cca = 0;
347 s32 val_sign32_tmp = 0;
348 u32 var[10] = {0};
349 u8 bw = *dm->band_width;
350
351 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) {
352 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
353 "Only Support for JGR-3 ICs\n");
354 return;
355 }
356
357 if (bw > 2) {
358 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
359 "Not Support for BW > %dM\n", 20 << bw);
360 return;
361 }
362
363 PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var[0]);
364 PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var[1]);
365 PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var[2]);
366
367 trig_time_cca = ((smp->smp_number_max >> (bw + 1)) / 10)
368 - (2 << (2 - bw)) - (2 - bw);
369
370 if (var[0] < 10) {
371 /*=== [Type: 0 ~ 10] : CCA P-edge trigger ==========================*/
372 /*--- Basic Trigger Setting --------------------------------*/
373 smp->la_trig_mode = 1;
374 smp->la_trig_sig_sel = 2;
375 smp->la_trigger_time = trig_time_cca;
376 smp->la_mac_mask_or_hdr_sel = 0;
377 smp->la_trigger_edge = 0;
378 smp->la_smp_rate = 2 - bw;
379 smp->la_count = 0;
380 if (var[0] == 0) { /*AGC*/
381 smp->la_dma_type = 5;
382 smp->la_dbg_port = 0x870;
383 } else if (var[0] == 1) { /*EVM*/
384 smp->la_dma_type = 4;
385 smp->la_dbg_port = 0x392;
386 } else if (var[0] == 2) { /*SNR*/
387 smp->la_dma_type = 4;
388 if (var[1] == 0)
389 smp->la_dbg_port = 0x89e;
390 else
391 smp->la_dbg_port = 0xa9e;
392 } else if (var[0] == 3) { /*CFO*/
393 smp->la_dma_type = 4;
394 if (var[1] == 0)
395 smp->la_dbg_port = 0x88c;
396 else
397 smp->la_dbg_port = 0xa8c;
398 } else if (var[0] == 4) { /*ADC*/
399 if (var[1] == 0) {
400 smp->la_dma_type = 0;
401 smp->la_dbg_port = 0x880;
402 } else {
403 smp->la_dma_type = 1;
404 smp->la_dbg_port = 0xa80;
405 }
406 }
407 /*--- Adv-Trigger Setting------------------------------------*/
408 adv->la_adv_bbtrigger_en = false;
409 } else if (var[0] < 20) {
410 /*=== [Type: 10 ~ 19]: RX-EVM Trigger ===============================*/
411 /*--- Basic Trigger Setting ---------------------------------*/
412 smp->la_trig_mode = 0;
413 smp->la_trig_sig_sel = 0;
414 smp->la_mac_mask_or_hdr_sel = 0;
415 smp->la_trigger_edge = 0;
416 smp->la_smp_rate = 2 - bw;
417 smp->la_count = 0;
418 smp->la_dma_type = 4;
419 smp->la_dbg_port = 0x392;
420
421 /*--- Adv-Trigger Setting -----------------------------------*/
422 phydm_la_bb_adv_reset_jgr3(dm);
423 adv->la_adv_bbtrigger_en = true;
424
425 /*And[0]*/
426 adv->la_ori_bb_dis = true;
427
428 /*And[1]*/
429 adv->la_and1_inv = 0;
430 adv->la_and1_sel = 4; /*RX-state*/
431 if (var[2] == 0) {
432 /*L-preamble 8+8+4 = 20*/
433 smp->la_trigger_time = trig_time_cca - 20;
434 /*Legacy Data*/
435 adv->la_and1_val = 5;
436 } else if (var[2] == 1) {
437 /*HT-preamble (8+8+4) + (8+4+4*Nrx) = 32 + Nrx * 4*/
438 smp->la_trigger_time = trig_time_cca - 32 -
439 (dm->num_rf_path * 4);
440 /*HT Data*/
441 adv->la_and1_val = 18;
442 } else {
443 /*VHT-preamble (8+8+4) + (8+4+4*Nrx) +4 = 36 + Nrx * 4*/
444 smp->la_trigger_time = trig_time_cca - 36 -
445 (dm->num_rf_path * 4);
446 /*VHT Data*/
447 adv->la_and1_val = 18;
448 }
449
450 /*And[2]*/
451 adv->la_and2_inv = 0;
452 adv->la_and2_sel = 0; /*Disable*/
453
454 /*And[3]*/
455 adv->la_and2_inv = 0;
456 adv->la_and3_sel = 0; /*Disable*/
457
458 /*And[4]*/
459 adv->la_and4_inv = 0;
460
461 if (var[0] == 11) {
462 /*[>= -X dB]*/
463 if (var[1] == 2) {
464 adv->la_and4_bitmap = 0;
465 adv->la_and4_mask = 0x1;
466 } else if (var[1] == 4) {
467 adv->la_and4_bitmap = 0;
468 adv->la_and4_mask = 0x3;
469 } else if (var[1] == 8) {
470 adv->la_and4_bitmap = 0;
471 adv->la_and4_mask = 0x7;
472 } else if (var[1] == 16) {
473 adv->la_and4_bitmap = 0;
474 adv->la_and4_mask = 0xf;
475 } else if (var[1] == 32) {
476 adv->la_and4_bitmap = 0;
477 adv->la_and4_mask = 0x1f;
478 } else if (var[1] == 64) {
479 adv->la_and4_bitmap = 0;
480 adv->la_and4_mask = 0x3f;
481 } else {
482 PDM_SNPF(*_out_len, *_used, output + *_used,
483 *_out_len - *_used,
484 "Not Support >= -%d dB\n", var[1]);
485 return;
486 }
487 } else if (var[0] == 10) {
488 /*[<= -X dB]*/
489 if (var[1] == 2) {
490 adv->la_and4_bitmap = 0x7e;
491 adv->la_and4_mask = 0x7e;
492 } else if (var[1] == 4) {
493 adv->la_and4_bitmap = 0x7c;
494 adv->la_and4_mask = 0x7c;
495 } else if (var[1] == 8) {
496 adv->la_and4_bitmap = 0x78;
497 adv->la_and4_mask = 0x78;
498 } else if (var[1] == 16) {
499 adv->la_and4_bitmap = 0x70;
500 adv->la_and4_mask = 0x70;
501 } else if (var[1] == 32) {
502 adv->la_and4_bitmap = 0x60;
503 adv->la_and4_mask = 0x60;
504 } else if (var[1] == 64) {
505 adv->la_and4_bitmap = 0x40;
506 adv->la_and4_mask = 0x40;
507 } else {
508 PDM_SNPF(*_out_len, *_used, output + *_used,
509 *_out_len - *_used,
510 "Not Support <= -%d dB\n", var[1]);
511 return;
512 }
513 } else if (var[0] == 12) {
514 /*[= -X dB]*/
515 val_sign32_tmp = 0 - (s32)var[1];
516 adv->la_and4_bitmap = (u32)(val_sign32_tmp & 0x7f);
517 adv->la_and4_mask = 0x7f;
518 }
519 } else if (var[0] < 30) {
520 /*=== [Type: 20 ~ 29]: RX-Rate Trigger ==============================*/
521 /*--- Basic Trigger Setting ---------------------------------*/
522 smp->la_trig_mode = 0;
523 smp->la_trig_sig_sel = 0;
524 smp->la_mac_mask_or_hdr_sel = 0;
525 smp->la_trigger_edge = 0;
526 smp->la_smp_rate = 2 - bw;
527 smp->la_count = 0;
528 smp->la_dma_type = 4;
529
530 rate_idx = (u8)var[1];
531
532 /*--- Adv-Trigger Setting -----------------------------------*/
533 phydm_la_bb_adv_reset_jgr3(dm);
534 adv->la_adv_bbtrigger_en = true;
535
536 /*And[0]*/
537 adv->la_ori_bb_dis = true;
538
539 /*And[1]*/
540 adv->la_and1_inv = 0;
541 adv->la_and1_sel = 4; /*RX-state*/
542
543 if (rate_idx <= ODM_RATE54M && rate_idx >= ODM_RATE6M) {
544 ad_mode = AD_LEGACY_MODE;
545 codeword = (u32)ofdm_codeword[rate_idx - ODM_RATE6M];
546 smp->la_dbg_port = 0x3a9;
547 /*L-preamble 8+8 = 16*/
548 smp->la_trigger_time = trig_time_cca - 20;
549 /*Legacy Data*/
550 adv->la_and1_val = 5;
551 } else if (rate_idx <= ODM_RATEMCS31) {
552 ad_mode = AD_HT_MODE;
553 codeword = (u32)(rate_idx - ODM_RATEMCS0);
554 smp->la_dbg_port = 0x3aa;
555 /*HT-preamble (8+8+4) + (8+4+4*Nrx) = 32 + Nrx * 4*/
556 smp->la_trigger_time = trig_time_cca - 32 -
557 (dm->num_rf_path * 4);
558 /*HT,VHT Data*/
559 adv->la_and1_val = 18;
560 } else if (rate_idx <= ODM_RATEVHTSS4MCS9) {
561 ad_mode = AD_VHT_MODE;
562 codeword = (u32)phydm_rate_order_compute(dm, rate_idx);
563 codeword--;
564 smp->la_dbg_port = 0x3ab;
565 /*VHT-preamble (8+8+4) + (8+4+4*Nrx) = 36 + Nrx * 4*/
566 smp->la_trigger_time = trig_time_cca - 36 -
567 (dm->num_rf_path * 4);
568 /*HT,VHT Data*/
569 adv->la_and1_val = 18;
570 } else {
571 PDM_SNPF(*_out_len, *_used, output + *_used,
572 *_out_len - *_used,
573 "Not Support\n");
574 return;
575 }
576
577 /*And[2]*/
578 adv->la_and2_inv = 0;
579 adv->la_and2_sel = 0; /*Disable*/
580
581 /*And[3]*/
582 adv->la_and2_inv = 0;
583 adv->la_and3_sel = 0; /*Disable*/
584
585 /*And[4]*/
586 adv->la_and4_inv = 0;
587
588 if (var[0] == 20) {
589 if (ad_mode == AD_LEGACY_MODE) {
590 adv->la_and4_bitmap = codeword;
591 adv->la_and4_mask = 0x3000000f;
592 } else if (ad_mode == AD_HT_MODE) {
593 adv->la_and4_bitmap = (2 << 28) | codeword;
594 adv->la_and4_mask = 0x3000003f;
595 } else { /* AD_VHT_MODE*/
596 adv->la_and4_bitmap = (1 << 28) |
597 (codeword << 4);
598 adv->la_and4_mask = 0x300000f0;
599 }
600 } else {
601 PDM_SNPF(*_out_len, *_used, output + *_used,
602 *_out_len - *_used,
603 "Not Support\n");
604 return;
605 }
606 } else {
607 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
608 "Not Support\n");
609 return;
610 }
611 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
612 "[Basic-Trigger]\n");
613 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
614 " *echo lamode 1 %d %d %d %d %d %x %d %d %d\n\n",
615 smp->la_trig_mode, smp->la_trig_sig_sel, smp->la_dma_type,
616 smp->la_trigger_time, smp->la_mac_mask_or_hdr_sel,
617 smp->la_dbg_port, smp->la_trigger_edge, smp->la_smp_rate,
618 smp->la_count);
619 pr_debug("echo lamode 1 %d %d %d %d %d %x %d %d %d\n\n",
620 smp->la_trig_mode, smp->la_trig_sig_sel, smp->la_dma_type,
621 smp->la_trigger_time, smp->la_mac_mask_or_hdr_sel,
622 smp->la_dbg_port, smp->la_trigger_edge, smp->la_smp_rate,
623 smp->la_count);
624
625 if (adv->la_adv_bbtrigger_en) {
626 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
627 "[Adv-Trigger]\n");
628 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
629 " *And0 Disable=%d\n", adv->la_ori_bb_dis);
630 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
631 " *And1{sel,val,inv}={0x%x,0x%x,%d}\n *And2{sel,val,inv}={0x%x,0x%x,%d}\n *And3{sel,val,inv}={0x%x,0x%x,%d}\n",
632 adv->la_and1_sel, adv->la_and1_val, adv->la_and1_inv,
633 adv->la_and2_sel, adv->la_and2_val, adv->la_and2_inv,
634 adv->la_and3_sel, adv->la_and3_val, adv->la_and3_inv);
635 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
636 " *And4{mask,bitmap,inv}={0x%x,0x%x,%d}\n",
637 adv->la_and4_mask, adv->la_and4_bitmap,
638 adv->la_and4_inv);
639 }
640 phydm_la_set(dm);
641 }
642
643 #endif
644
645 void
phydm_la_buffer_print(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)646 phydm_la_buffer_print(void *dm_void, char input[][16], u32 *_used,
647 char *output, u32 *_out_len)
648 {
649 struct dm_struct *dm = (struct dm_struct *)dm_void;
650 struct rt_adcsmp *smp = &dm->adcsmp;
651 struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
652 u64 la_pattern_msb, la_pattern_lsb;
653 u64 la_pattern, la_pattern_part;
654 s64 tmp_s64;
655 u64 mask = 0xffffffff;
656 u8 mask_length = 0;
657 u32 i;
658 u32 idx;
659 u32 var[10] = {0};
660
661 if (!buf->octet || buf->length == 0 || buf->length < smp->smp_number)
662 return;
663
664 PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var[0]);
665 PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var[1]);
666 PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var[2]);
667 PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var[3]);
668
669 pr_debug("echo lamode 1 %d %d %d %d %d %x %d %d %d\n\n",
670 smp->la_trig_mode, smp->la_trig_sig_sel, smp->la_dma_type,
671 smp->la_trigger_time, smp->la_mac_mask_or_hdr_sel,
672 smp->la_dbg_port, smp->la_trigger_edge, smp->la_smp_rate,
673 smp->la_count);
674 pr_debug("[LA Data Dump] smp_number = %d\n", smp->smp_number);
675 pr_debug("Dump_Start\n");
676
677 if (var[0] == 0) {
678 for (i = 0; i < smp->smp_number; i++) {
679 idx = i << 1;
680 pr_debug("%08x%08x\n", buf->octet[idx],
681 buf->octet[idx + 1]);
682 }
683 } else if (var[0] == 1) {
684 /*------------------------*/
685 if (var[1] == 0)
686 pr_debug("[Hex]\n");
687 else if (var[1] == 1)
688 pr_debug("[Dec unsigned]\n");
689 else if (var[1] == 2)
690 pr_debug("[Dec signed]\n");
691
692 pr_debug("BIT[%d:%d]\n", var[3], var[2]);
693
694 if (var[2] > var[3]) {
695 pr_debug("[Warning] BIT_L > BIT_H\n");
696 return;
697 }
698
699 mask_length = (u8)(var[3] - var[2] + 1);
700 mask = phydm_gen_bitmask(mask_length) << var[2];
701 /*------------------------*/
702 for (i = 0; i < smp->smp_number; i++) {
703 idx = i << 1;
704 la_pattern_msb = (u64)buf->octet[idx];
705 la_pattern_lsb = (u64)buf->octet[idx + 1];
706 la_pattern = (la_pattern_msb << 32) | la_pattern_lsb;
707 la_pattern_part = (la_pattern & mask) >> var[2];
708
709 if (var[1] == 0) {
710 pr_debug("0x%llx\n", la_pattern_part);
711 } else if (var[1] == 1) {
712 pr_debug("%llu\n", la_pattern_part);
713 } else if (var[1] == 2) {
714 tmp_s64 = phydm_cnvrt_2_sign_64(la_pattern_part,
715 mask_length);
716 pr_debug("%lld\n", tmp_s64);
717 }
718 }
719 }
720 pr_debug("Dump_End\n\n");
721 }
722
723 void
phydm_la_buffer_release(void * dm_void)724 phydm_la_buffer_release(void *dm_void)
725 {
726 struct dm_struct *dm = (struct dm_struct *)dm_void;
727 struct rt_adcsmp *smp = &dm->adcsmp;
728 struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
729
730 if (buf->length != 0x0) {
731 odm_free_memory(dm, buf->octet, buf->length);
732 buf->length = 0x0;
733 }
734 }
735
736 boolean
phydm_la_buffer_allocate(void * dm_void)737 phydm_la_buffer_allocate(void *dm_void)
738 {
739 struct dm_struct *dm = (struct dm_struct *)dm_void;
740 struct rt_adcsmp *smp = &dm->adcsmp;
741 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
742 void *adapter = dm->adapter;
743 #endif
744 struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
745 boolean ret = true;
746
747 pr_debug("[LA mode BufferAllocate]\n");
748
749 if (buf->length == 0) {
750 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
751 if (PlatformAllocateMemoryWithZero(adapter, (void **)&
752 buf->octet,
753 buf->buffer_size) !=
754 RT_STATUS_SUCCESS)
755 ret = false;
756 #else
757 odm_allocate_memory(dm, (void **)&buf->octet, buf->buffer_size);
758
759 if (!buf->octet)
760 ret = false;
761 #endif
762
763 if (ret)
764 buf->length = buf->buffer_size;
765 }
766
767 return ret;
768 }
769
phydm_la_access_tx_pkt_buf(void * dm_void,u32 addr,u32 buff_idx)770 void phydm_la_access_tx_pkt_buf(void *dm_void, u32 addr, u32 buff_idx)
771 {
772 struct dm_struct *dm = (struct dm_struct *)dm_void;
773 struct rt_adcsmp *smp = &dm->adcsmp;
774 struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
775 u32 page;
776 u32 data_l = 0, data_h = 0;
777
778 #if (RTL8192F_SUPPORT)
779 if (dm->support_ic_type & ODM_RTL8192F) {
780 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
781 indirect_access_sdram_8192f(dm->adapter, TX_PACKET_BUFFER,
782 TRUE, (u16)addr >> 3, 0,
783 &data_h, &data_l);
784 #else
785 odm_write_1byte(dm, R_0x0106, 0x69);
786 odm_set_mac_reg(dm, R_0x0140, MASKDWORD, addr >> 3);
787 data_l = odm_get_mac_reg(dm, R_0x0144, MASKDWORD);
788 data_h = odm_get_mac_reg(dm, R_0x0148, MASKDWORD);
789 odm_write_1byte(dm, R_0x0106, 0x0);
790 #endif
791 } else
792 #endif
793 {
794 /* Reg140=0x780+(addr>>12),
795 * addr=0x30~0x3F, total 16 pages
796 */
797 page = addr >> 12;
798
799 if (page != smp->txff_page) {
800 smp->txff_page = page;
801 odm_set_mac_reg(dm, R_0x0140, MASKLWORD, 0x780 + page);
802 }
803 data_l = odm_read_4byte(dm, R_0x8000 + (addr & 0xfff));
804 data_h = odm_read_4byte(dm, R_0x8000 + (addr & 0xfff) + 4);
805 }
806
807 buf->octet[buff_idx] = data_h;
808 buf->octet[buff_idx + 1] = data_l;
809
810 /*@==== [Print LA Patterns] ==========================================*/
811 if (smp->is_la_print)
812 pr_debug("%08x%08x\n", data_h, data_l);
813 }
814
phydm_la_get_tx_pkt_buf(void * dm_void)815 void phydm_la_get_tx_pkt_buf(void *dm_void)
816 {
817 struct dm_struct *dm = (struct dm_struct *)dm_void;
818 struct rt_adcsmp *smp = &dm->adcsmp;
819 struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
820 u32 i = 0, value32 = 0;
821 u32 addr = 0, finish_addr = 0; /* @(unit: 8Byte)*/
822 boolean is_round_up = false;
823 u32 addr_8byte = 0;
824 u32 round_up_point = 0;
825 #if (RTL8814B_SUPPORT)
826 boolean recover_success = true;
827 #endif
828
829 odm_memory_set(dm, buf->octet, 0, buf->length);
830 pr_debug("GetTxPktBuf\n");
831
832 /*@==== [Get LA Report] ==============================================*/
833 if (dm->support_ic_type & ODM_RTL8192F) {
834 value32 = odm_read_4byte(dm, R_0x7f0);
835 is_round_up = (boolean)((value32 & BIT(31)) >> 31);
836 finish_addr = (value32 & 0x7FFF8000) >> 15; /*@16 bit (unit: 8Byte)*/
837 } else {
838 odm_write_1byte(dm, R_0x0106, 0x69);
839 value32 = odm_read_4byte(dm, R_0x7c0);
840 is_round_up = (boolean)((value32 & BIT(31)) >> 31);
841
842 if (dm->support_ic_type & PHYDM_LA_STORE_IN_IMEM_IC)
843 finish_addr = (value32 & 0x7FFF8000) >> 15; /*@16 bit (unit: 8Byte)*/
844 else
845 finish_addr = (value32 & 0x7FFF0000) >> 16; /*@15bit (unit: 8Byte)*/
846 }
847
848 #if (RTL8814B_SUPPORT)
849 recover_success = phydm_la_finish_addr_recover_8814B(dm, &finish_addr);
850 #endif
851
852 pr_debug("start_addr = ((0x%x)), end_addr = ((0x%x)), buffer_size = ((0x%x))\n",
853 buf->start_pos, buf->end_pos, buf->buffer_size);
854 if (is_round_up) {
855 pr_debug("buf_start(0x%x)|----2---->|finish_addr(0x%x)|----1---->|buf_end(0x%x)\n",
856 buf->start_pos, finish_addr << 3, buf->end_pos);
857 addr = (finish_addr + 2) << 3; /*+1 or +2 ??*/
858 round_up_point = (buf->end_pos - addr) >> 3; /*@Byte to 8Byte*/
859 smp->smp_number = smp->smp_number_max;
860 pr_debug("is_round_up=(%d), round_up_point=(%d), 0x7c0/0x7F0=(0x%x), smp_number=(%d)\n",
861 is_round_up, round_up_point, value32, smp->smp_number);
862 } else {
863 pr_debug("buf_start(0x%x)|------->|finish_addr(0x%x) |buf_end(0x%x)\n",
864 buf->start_pos, finish_addr << 3, buf->end_pos);
865 addr = buf->start_pos;
866 addr_8byte = addr >> 3;
867 smp->smp_number = DIFF_2(addr_8byte, finish_addr);
868
869 pr_debug("is_round_up=(%d), smp_number=(%d)\n",
870 is_round_up, smp->smp_number);
871 }
872
873 /*@==== [Get LA Patterns in TXFF] ====================================*/
874 pr_debug("Dump_Start\n");
875 #ifdef PHYDM_COMPILE_LA_STORE_IN_IMEM
876 phydm_la_mv_data_2_tx_buffer(dm);
877 #endif
878
879 #if (RTL8814B_SUPPORT)
880 if ((dm->support_ic_type & ODM_RTL8814B) && !recover_success) {
881 addr = buf->start_pos;
882 smp->smp_number = smp->smp_number_max;
883 }
884 #endif
885
886 for (i = 0; i < smp->smp_number; i++) {
887 phydm_la_access_tx_pkt_buf(dm, addr, i << 1);
888 addr += 8;
889
890 if (addr >= buf->end_pos)
891 addr = buf->start_pos; /*Ring buffer*/
892 }
893
894 #if (RTL8197F_SUPPORT)
895 phydm_la_stop_dma_8197f(dm, PHYDM_RESTORE);
896 #endif
897 pr_debug("Dump_End\n");
898 }
899
phydm_la_set_trig_src(void * dm_void,u8 la_trig_mode)900 void phydm_la_set_trig_src(void *dm_void, u8 la_trig_mode)
901 {
902 struct dm_struct *dm = (struct dm_struct *)dm_void;
903 u32 reg = (dm->support_ic_type == ODM_RTL8192F) ? R_0x7f0 : R_0x7c0;
904
905 if (la_trig_mode == PHYDM_ADC_MAC_TRIG)
906 odm_set_mac_reg(dm, reg, BIT(3), 1);
907 else
908 odm_set_mac_reg(dm, reg, BIT(3), 0);
909 }
910
phydm_la_set_mac_iq_dump(void * dm_void,boolean impossible_trig_condi)911 void phydm_la_set_mac_iq_dump(void *dm_void, boolean impossible_trig_condi)
912 {
913 struct dm_struct *dm = (struct dm_struct *)dm_void;
914 struct rt_adcsmp *smp = &dm->adcsmp;
915 u32 reg_value = 0;
916 u32 reg1 = 0, reg2 = 0, reg3 = 0;
917
918 if (dm->support_ic_type & ODM_RTL8192F) {
919 reg1 = R_0x7f0;
920 reg2 = R_0x7f4;
921 reg3 = R_0x7f8;
922 } else {
923 reg1 = R_0x7c0;
924 reg2 = R_0x7c4;
925 reg3 = R_0x7c8;
926 }
927
928 odm_write_1byte(dm, reg1, 0); /*@clear all reg1*/
929 /*@Enable LA mode HW block*/
930 odm_set_mac_reg(dm, reg1, BIT(0), 1);
931
932 if (smp->la_trig_mode == PHYDM_MAC_TRIG) {
933 smp->la_dump_mode = LA_MAC_DBG_DUMP;
934 /*polling bit for MAC mode*/
935 odm_set_mac_reg(dm, reg1, BIT(2), 1);
936 /*trigger mode for MAC*/
937 odm_set_mac_reg(dm, reg1, 0x18, smp->la_trigger_edge);
938 pr_debug("[MAC_trig] ref_mask=(0x%x), ref_value=(0x%x), dbg_port =(0x%x)\n",
939 smp->la_mac_mask_or_hdr_sel, smp->la_trig_sig_sel,
940 smp->la_dbg_port);
941 /*@[Set MAC Debug Port]*/
942 odm_set_mac_reg(dm, R_0xf4, BIT(16), 1);
943 odm_set_mac_reg(dm, R_0x38, 0xff0000, smp->la_dbg_port);
944 odm_set_mac_reg(dm, reg2, MASKDWORD,
945 smp->la_mac_mask_or_hdr_sel);
946 odm_set_mac_reg(dm, reg3, MASKDWORD, smp->la_trig_sig_sel);
947 } else {
948 smp->la_dump_mode = LA_BB_ADC_DUMP;
949
950 if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) {
951 /*polling bit for MAC trigger event*/
952 if (impossible_trig_condi)
953 phydm_la_set_trig_src(dm, PHYDM_ADC_BB_TRIG);
954 else
955 phydm_la_set_trig_src(dm, PHYDM_ADC_MAC_TRIG);
956
957 odm_set_mac_reg(dm, reg1, 0xc0, smp->la_trig_sig_sel);
958
959 if (smp->la_trig_sig_sel == ADCSMP_TRIG_REG) {
960 /* @manual trigger reg1[5] = 0->1*/
961 odm_set_mac_reg(dm, reg1, BIT(5), 1);
962 }
963 }
964 /*polling bit for BB ADC mode*/
965 odm_set_mac_reg(dm, reg1, BIT(1), 1);
966 }
967
968 reg_value = odm_get_mac_reg(dm, reg1, 0xff);
969 pr_debug("4. [Set MAC IQ dump] 0x%x[7:0]=(0x%x)\n", reg1, reg_value);
970
971 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
972 RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
973 ("4. [Set MAC IQ dump] 0x%x[7:0]=(0x%x)\n", reg1,
974 reg_value));
975 #endif
976 }
977
phydm_la_set_bb_dbg_port(void * dm_void,boolean impossible_trig_condi)978 void phydm_la_set_bb_dbg_port(void *dm_void, boolean impossible_trig_condi)
979 {
980 struct dm_struct *dm = (struct dm_struct *)dm_void;
981 struct rt_adcsmp *smp = &dm->adcsmp;
982
983 u8 trig_mode = smp->la_trig_mode;
984 u32 trig_sel = smp->la_trig_sig_sel;
985 u32 dbg_port = smp->la_dbg_port;
986
987 if (trig_mode == PHYDM_MAC_TRIG)
988 trig_sel = 0; /*@ignore this setting*/
989
990 /*set BB debug port*/
991 if (impossible_trig_condi) {
992 dbg_port = 0xf;
993 trig_sel = 0;
994 pr_debug("[BB Setting] fake-trigger!\n");
995 }
996
997 if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbg_port)) {
998 pr_debug(" *Set dbg_port=(0x%x)\n", dbg_port);
999 } else {
1000 dbg_port = phydm_get_bb_dbg_port_idx(dm);
1001 pr_debug("[Set dbg_port fail!] Curr-DbgPort=0x%x\n", dbg_port);
1002 }
1003
1004 /*@debug port bit*/
1005 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
1006 odm_set_bb_reg(dm, R_0x95c, 0x1f, trig_sel);
1007 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
1008 } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1009 odm_set_bb_reg(dm, R_0x1ce4, 0x3e000, trig_sel);
1010 #endif
1011 } else {
1012 odm_set_bb_reg(dm, R_0x9a0, 0x1f, trig_sel);
1013 }
1014
1015 if (smp->la_trig_mode == PHYDM_ADC_BB_TRIG) {
1016 pr_debug(" *Set dbg_port[BIT] = %d\n", trig_sel);
1017
1018 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1019 RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
1020 (" *Set dbg_port[BIT] = %d\n", trig_sel));
1021 #endif
1022 }
1023 }
1024
phydm_la_set_bb(void * dm_void)1025 void phydm_la_set_bb(void *dm_void)
1026 {
1027 struct dm_struct *dm = (struct dm_struct *)dm_void;
1028 struct rt_adcsmp *smp = &dm->adcsmp;
1029
1030 u8 trig_mode = smp->la_trig_mode;
1031 u8 edge = smp->la_trigger_edge;
1032 u8 smp_rate = smp->la_smp_rate;
1033 u8 dma_type = smp->la_dma_type;
1034 u32 dbg_port_hdr_sel = 0;
1035 char *trig_mode_word = NULL;
1036
1037 pr_debug("3. [BB Setting] mode=(%d), Edge=(%s), smp_rate=(%dM), Dma_type=(%d)\n",
1038 trig_mode,
1039 (edge == 0) ? "P" : "N", 80 >> smp_rate, dma_type);
1040
1041 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
1042 if (trig_mode == PHYDM_ADC_RF0_TRIG)
1043 dbg_port_hdr_sel = 9; /*@DBGOUT_RFC_a[31:0]*/
1044 else if (trig_mode == PHYDM_ADC_RF1_TRIG)
1045 dbg_port_hdr_sel = 8; /*@DBGOUT_RFC_b[31:0]*/
1046 else if ((trig_mode == PHYDM_ADC_BB_TRIG) ||
1047 (trig_mode == PHYDM_ADC_MAC_TRIG)) {
1048 if (smp->la_mac_mask_or_hdr_sel <= 0xf)
1049 dbg_port_hdr_sel = smp->la_mac_mask_or_hdr_sel;
1050 else
1051 dbg_port_hdr_sel = 0;
1052 }
1053
1054 phydm_bb_dbg_port_header_sel(dm, dbg_port_hdr_sel);
1055
1056 odm_set_bb_reg(dm, R_0x8b4, BIT(7), 1);/*@update rpt every pkt*/
1057 odm_set_bb_reg(dm, R_0x95c, 0xf00, dma_type);
1058 /*@0: posedge, 1: negedge*/
1059 odm_set_bb_reg(dm, R_0x95c, BIT(31), edge);
1060 odm_set_bb_reg(dm, R_0x95c, 0xe0, smp_rate);
1061 /* @(0:) '80MHz'
1062 * (1:) '40MHz'
1063 * (2:) '20MHz'
1064 * (3:) '10MHz'
1065 * (4:) '5MHz'
1066 * (5:) '2.5MHz'
1067 * (6:) '1.25MHz'
1068 * (7:) '160MHz (for BW160 ic)'
1069 */
1070 #if (RTL8821C_SUPPORT || RTL8195B_SUPPORT)
1071 phydm_la_clk_en(dm, true);
1072 #endif
1073
1074 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
1075 } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1076 odm_set_bb_reg(dm, R_0x1eb4, BIT(23), 0x1);/*@update rpt every pkt*/
1077 /*@MAC-PHY timing*/
1078 odm_set_bb_reg(dm, R_0x1ce4, BIT(7) | BIT(6), 0);
1079 odm_set_bb_reg(dm, R_0x1cf4, BIT(23), 1); /*@LA mode on*/
1080 odm_set_bb_reg(dm, R_0x1ce4, 0x3f, dma_type);
1081 /*@0: posedge, 1: negedge ??*/
1082 odm_set_bb_reg(dm, R_0x1ce4, BIT(26), edge);
1083 odm_set_bb_reg(dm, R_0x1ce4, 0x700, smp_rate);
1084
1085 phydm_la_bb_adv_trig_setting_jgr3(dm);
1086 #endif
1087 } else {
1088 if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
1089 odm_set_bb_reg(dm, R_0xd00, BIT(26), 0x1); /*@update rpt every pkt*/
1090
1091 #if (RTL8192F_SUPPORT)
1092 if ((dm->support_ic_type & ODM_RTL8192F))
1093 /*@LA reset HW block enable for true-mac asic*/
1094 odm_set_bb_reg(dm, R_0x9a0, BIT(15), 1);
1095 #endif
1096
1097 odm_set_bb_reg(dm, R_0x9a0, 0xf00, dma_type);
1098 /*@0: posedge, 1: negedge*/
1099 odm_set_bb_reg(dm, R_0x9a0, BIT(31), edge);
1100 odm_set_bb_reg(dm, R_0x9a0, 0xe0, smp_rate);
1101 /* @(0:) '80MHz'
1102 * (1:) '40MHz'
1103 * (2:) '20MHz'
1104 * (3:) '10MHz'
1105 * (4:) '5MHz'
1106 * (5:) '2.5MHz'
1107 * (6:) '1.25MHz'
1108 * (7:) '160MHz (for BW160 ic)'
1109 */
1110 }
1111 }
1112
phydm_la_set_mac_trigger_time(void * dm_void,u32 trigger_time_mu_sec)1113 void phydm_la_set_mac_trigger_time(void *dm_void, u32 trigger_time_mu_sec)
1114 {
1115 struct dm_struct *dm = (struct dm_struct *)dm_void;
1116 u8 time_unit_num = 0;
1117 u32 unit = 0;
1118
1119 if (trigger_time_mu_sec < 128)
1120 unit = 0; /*unit: 1mu sec*/
1121 else if (trigger_time_mu_sec < 256)
1122 unit = 1; /*unit: 2mu sec*/
1123 else if (trigger_time_mu_sec < 512)
1124 unit = 2; /*unit: 4mu sec*/
1125 else if (trigger_time_mu_sec < 1024)
1126 unit = 3; /*unit: 8mu sec*/
1127 else if (trigger_time_mu_sec < 2048)
1128 unit = 4; /*unit: 16mu sec*/
1129 else if (trigger_time_mu_sec < 4096)
1130 unit = 5; /*unit: 32mu sec*/
1131 else if (trigger_time_mu_sec < 8192)
1132 unit = 6; /*unit: 64mu sec*/
1133
1134 time_unit_num = (u8)(trigger_time_mu_sec >> unit);
1135
1136 pr_debug("2. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n",
1137 time_unit_num, unit);
1138 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1139 RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, (
1140 "3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n",
1141 time_unit_num, unit));
1142 #endif
1143
1144 if (dm->support_ic_type & ODM_RTL8192F) {
1145 odm_set_mac_reg(dm, R_0x7fc, BIT(2) | BIT(1) | BIT(0), unit);
1146 odm_set_mac_reg(dm, R_0x7f0, 0x7f00, (time_unit_num & 0x7f));
1147 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
1148 } else if (dm->support_ic_type & ODM_RTL8814B) {
1149 odm_set_mac_reg(dm, R_0x7cc, BIT(20) | BIT(19) | BIT(18), unit);
1150 odm_set_mac_reg(dm, R_0x7c0, 0x7f00, (time_unit_num & 0x7f));
1151 } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1152 odm_set_mac_reg(dm, R_0x7cc, BIT(18) | BIT(17) | BIT(16), unit);
1153 odm_set_mac_reg(dm, R_0x7c0, 0x7f00, (time_unit_num & 0x7f));
1154 #endif
1155 } else {
1156 odm_set_mac_reg(dm, R_0x7cc, BIT(20) | BIT(19) | BIT(18), unit);
1157 odm_set_mac_reg(dm, R_0x7c0, 0x7f00, (time_unit_num & 0x7f));
1158 }
1159 }
1160
phydm_la_set_buff_mode(void * dm_void,enum la_buff_mode mode)1161 void phydm_la_set_buff_mode(void *dm_void, enum la_buff_mode mode)
1162 {
1163 struct dm_struct *dm = (struct dm_struct *)dm_void;
1164 struct rt_adcsmp *smp = &dm->adcsmp;
1165 struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
1166 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
1167 struct rtl8192cd_priv *priv = dm->priv;
1168 u8 normal_LA_on = priv->pmib->miscEntry.normal_LA_on;
1169 #endif
1170 u32 buff_size_base = 0;
1171 u32 end_pos_tmp = 0;
1172
1173 smp->la_buff_mode = mode;
1174 switch (dm->support_ic_type) {
1175 case ODM_RTL8814A:
1176 buff_size_base = 0x10000;
1177 end_pos_tmp = 0x40000;
1178 break;
1179 case ODM_RTL8822B:
1180 case ODM_RTL8822C:
1181 case ODM_RTL8812F:
1182 buff_size_base = 0x20000; /*@WIN: TX_FIFO_SIZE_LA_8822C*/
1183 end_pos_tmp = 0x40000;
1184 break;
1185 case ODM_RTL8814B:
1186 buff_size_base = 0x30000;
1187 end_pos_tmp = 0x60000;
1188 break;
1189 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
1190 case ODM_RTL8197F:
1191 case ODM_RTL8198F:
1192 case ODM_RTL8197G:
1193 buff_size_base = 0x10000;
1194 end_pos_tmp = (normal_LA_on == 1) ? 0x20000 : 0x10000;
1195 break;
1196 #endif
1197 case ODM_RTL8192F:
1198 buff_size_base = 0xE000;
1199 end_pos_tmp = 0x10000;
1200 break;
1201 case ODM_RTL8821C:
1202 buff_size_base = 0x8000;
1203 end_pos_tmp = 0x10000;
1204 break;
1205 case ODM_RTL8195B:
1206 buff_size_base = 0x4000;
1207 end_pos_tmp = 0x8000;
1208 break;
1209 default:
1210 pr_debug("[%s] Warning!", __func__);
1211 break;
1212 }
1213
1214 buf->buffer_size = buff_size_base;
1215
1216 if (dm->support_ic_type & ODM_RTL8814B) {
1217 if (mode == ADCSMP_BUFF_HALF) {
1218 odm_set_mac_reg(dm, R_0x7cc, BIT(21), 0);
1219 } else {
1220 buf->buffer_size = buf->buffer_size << 1;
1221 odm_set_mac_reg(dm, R_0x7cc, BIT(21), 1);
1222 }
1223 } else if (dm->support_ic_type & FULL_BUFF_MODE_SUPPORT) {
1224 if (mode == ADCSMP_BUFF_HALF) {
1225 odm_set_mac_reg(dm, R_0x7cc, BIT(30), 0);
1226 } else {
1227 buf->buffer_size = buf->buffer_size << 1;
1228 odm_set_mac_reg(dm, R_0x7cc, BIT(30), 1);
1229 }
1230 }
1231
1232 buf->end_pos = end_pos_tmp;
1233 buf->start_pos = end_pos_tmp - buf->buffer_size;
1234 smp->smp_number_max = buf->buffer_size >> 3;
1235
1236 pr_debug("start_addr=(0x%x), end_addr=(0x%x), buffer_size=(0x%x), smp_number_max=(%d)\n",
1237 buf->start_pos, buf->end_pos, buf->buffer_size,
1238 smp->smp_number_max);
1239 }
1240
phydm_la_adc_smp_start(void * dm_void)1241 void phydm_la_adc_smp_start(void *dm_void)
1242 {
1243 struct dm_struct *dm = (struct dm_struct *)dm_void;
1244 struct rt_adcsmp *smp = &dm->adcsmp;
1245 u8 tmp_u1b = 0;
1246 u8 i = 0;
1247 u8 polling_bit = 0;
1248 boolean polling_ok = false;
1249 boolean impossible_trig_condi = (smp->en_fake_trig) ? true : false;
1250
1251 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1252 RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
1253 ("1. [BB Setting] Mode=(%d), DbgPort=(0x%x), Edge=(%d), SmpRate=(%d), Trig_Sel=(0x%x), Dma_type=(%d)\n",
1254 smp->la_trig_mode, smp->la_dbg_port, smp->la_trigger_edge,
1255 smp->la_smp_rate, smp->la_trig_sig_sel, smp->la_dma_type));
1256 #endif
1257 pr_debug("1. [BB Setting] trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x)), Dma_type = ((%d))\n",
1258 smp->la_trig_mode, smp->la_dbg_port, smp->la_trigger_edge,
1259 smp->la_smp_rate, smp->la_trig_sig_sel, smp->la_dma_type);
1260
1261 phydm_la_set_mac_trigger_time(dm, smp->la_trigger_time);
1262 phydm_la_set_bb(dm);
1263 phydm_la_set_bb_dbg_port(dm, impossible_trig_condi);
1264 phydm_la_set_mac_iq_dump(dm, impossible_trig_condi);
1265
1266 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1267 watchdog_stop(dm->priv);
1268 #endif
1269
1270 if (impossible_trig_condi) {
1271 ODM_delay_ms(100);
1272 phydm_la_set_bb_dbg_port(dm, false);
1273
1274 if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) {
1275 phydm_la_set_trig_src(dm, PHYDM_ADC_MAC_TRIG);
1276 }
1277 }
1278 #if RTL8198F_SUPPORT
1279 phydm_la_pre_run(dm);
1280 #endif
1281 polling_bit = (smp->la_dump_mode == LA_BB_ADC_DUMP) ? BIT(1) : BIT(2);
1282 do { /*Polling time always use 100ms, when it exceed 2s, break loop*/
1283 if (dm->support_ic_type & ODM_RTL8192F)
1284 tmp_u1b = odm_read_1byte(dm, R_0x7f0);
1285 else
1286 tmp_u1b = odm_read_1byte(dm, R_0x7c0);
1287
1288 pr_debug("[%d] polling rpt=((0x%x))\n", i, tmp_u1b);
1289
1290 if (smp->adc_smp_state != ADCSMP_STATE_SET) {
1291 pr_debug("[state Error] state != ADCSMP_STATE_SET\n");
1292 break;
1293
1294 } else if (tmp_u1b & polling_bit) {
1295 ODM_delay_ms(100);
1296 i++;
1297 continue;
1298 } else {
1299 pr_debug("[LA Query OK] polling_bit=%d\n", polling_bit);
1300 polling_ok = true;
1301 break;
1302 }
1303 } while (i < 20);
1304
1305 if (smp->adc_smp_state == ADCSMP_STATE_SET) {
1306 if (polling_ok)
1307 phydm_la_get_tx_pkt_buf(dm);
1308 else
1309 pr_debug("[Polling timeout]\n");
1310 }
1311
1312 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1313 watchdog_resume(dm->priv);
1314 #endif
1315
1316 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1317 if (smp->adc_smp_state == ADCSMP_STATE_SET)
1318 smp->adc_smp_state = ADCSMP_STATE_QUERY;
1319 #endif
1320
1321 pr_debug("[LA mode] la_count = ((%d))\n", smp->la_count);
1322 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1323 RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
1324 ("[LA mode] la_count = ((%d))\n", smp->la_count));
1325 #endif
1326
1327 phydm_la_stop(dm);
1328
1329 if (smp->la_count == 0) {
1330 pr_debug("LA Dump finished ---------->\n\n\n");
1331 phydm_release_bb_dbg_port(dm);
1332
1333 #if (RTL8821C_SUPPORT || RTL8195B_SUPPORT)
1334 phydm_la_clk_en(dm, false);
1335 #endif
1336 } else {
1337 smp->la_count--;
1338 pr_debug("LA Dump more ---------->\n\n\n");
1339 phydm_la_set(dm);
1340 }
1341 }
1342
phydm_la_set(void * dm_void)1343 void phydm_la_set(void *dm_void)
1344 {
1345 struct dm_struct *dm = (struct dm_struct *)dm_void;
1346 boolean is_set_success = true;
1347 struct rt_adcsmp *smp = &dm->adcsmp;
1348
1349 if (smp->adc_smp_state != ADCSMP_STATE_IDLE)
1350 is_set_success = false;
1351 else if (smp->adc_smp_buf.length == 0)
1352 is_set_success = phydm_la_buffer_allocate(dm);
1353
1354 if (!is_set_success) {
1355 pr_debug("[LA Set Fail] LA_State=(%d)\n", smp->adc_smp_state);
1356 return;
1357 }
1358
1359 smp->adc_smp_state = ADCSMP_STATE_SET;
1360
1361 pr_debug("[LA Set Success] LA_State=(%d)\n", smp->adc_smp_state);
1362
1363 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1364
1365 pr_debug("ADCSmp_work_item_index=(%d)\n", smp->la_work_item_index);
1366
1367 if (smp->la_work_item_index != 0) {
1368 odm_schedule_work_item(&smp->adc_smp_work_item_1);
1369 smp->la_work_item_index = 0;
1370 } else {
1371 odm_schedule_work_item(&smp->adc_smp_work_item);
1372 smp->la_work_item_index = 1;
1373 }
1374 #else
1375 phydm_la_adc_smp_start(dm);
1376 #endif
1377 }
1378
phydm_la_cmd(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)1379 void phydm_la_cmd(void *dm_void, char input[][16], u32 *_used, char *output,
1380 u32 *_out_len)
1381 {
1382 struct dm_struct *dm = (struct dm_struct *)dm_void;
1383 struct rt_adcsmp *smp = &dm->adcsmp;
1384 char help[] = "-h";
1385 u32 var1[10] = {0};
1386 u32 used = *_used;
1387 u32 out_len = *_out_len;
1388
1389 if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE))
1390 return;
1391
1392 #ifdef PHYDM_COMPILE_LA_STORE_IN_IMEM
1393 if (dm->support_ic_type & PHYDM_LA_STORE_IN_IMEM_IC) {
1394 if (dm->is_download_fw)
1395 return;
1396 }
1397 #if RTL8198F_SUPPORT
1398 if (dm->support_ic_type & ODM_RTL8198F) {
1399 if (!*dm->mp_mode && !dm->priv->pmib->miscEntry.normal_LA_on) {
1400 pr_debug("plz re-set normal_LA_on = 1 & DnUp.\n");
1401 return;
1402 }
1403 }
1404 #endif
1405 #endif
1406
1407 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
1408
1409 /*@dbg_print("echo cmd input_num = %d\n", input_num);*/
1410
1411 if ((strcmp(input[1], help) == 0)) {
1412 PDM_SNPF(out_len, used, output + used, out_len - used,
1413 "=====[LA Mode Help] =============================\n");
1414 /*Trigger*/
1415 PDM_SNPF(out_len, used, output + used, out_len - used,
1416 "BB_trig: 1 0 {DbgPort Bit} {DMA#} {TrigTime} {DbgPort_head(Jgr2)}\n\t{DbgPort} {Edge: 0(P),1(N)} {f_smp:80 >> N} {Capture num}\n\n");
1417 PDM_SNPF(out_len, used, output + used, out_len - used,
1418 "MAC_trig: 1 1 {0-ok/1-fail/2-cca} {DMA#} {TrigTime} {DbgPort_head(Jgr2)}\n\t{DbgPort} {N/A} {f_smp:80 >> N} {Cpture num}\n\n");
1419 PDM_SNPF(out_len, used, output + used, out_len - used,
1420 "All: {En} {0:ADC_BB_trig,1:ADC MAC_trig,2:RF0,3:RF1,4:MAC}\n\t{BB:dbg_port[bit],BB_MAC:0-ok/1-fail/2-cca,MAC:ref} {DMA#} {TrigTime}\n\t{DbgPort_head/ref_mask} {dbg_port} {0:P_Edge, 1:N_Edge} {SpRate:0-80M,1-40M,2-20M} {Capture num}\n\n");
1421 /*Adv-Trig*/
1422 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
1423 PDM_SNPF(out_len, used, output + used, out_len - used,
1424 "adv show\n");
1425 PDM_SNPF(out_len, used, output + used, out_len - used,
1426 "adv {adv_trig_en} {0:And[0]_disable} {en}\n");
1427 PDM_SNPF(out_len, used, output + used, out_len - used,
1428 "adv {adv_trig_en} {1~3: And[3:0]} {Sel} {Val} {Inv}\n");
1429 PDM_SNPF(out_len, used, output + used, out_len - used,
1430 "adv {adv_trig_en} {4: And[4]} {BitMask} {BitVal} {Inv}\n\n");
1431 #endif
1432 /*Setting*/
1433 PDM_SNPF(out_len, used, output + used, out_len - used,
1434 "set {1:tx_buff_size} {0: half, 1:full}\n");
1435 PDM_SNPF(out_len, used, output + used, out_len - used,
1436 "set {2:Fake Trigger} {en}\n");
1437 PDM_SNPF(out_len, used, output + used, out_len - used,
1438 "set {3:Auto Print} {en}\n\n");
1439 /*Print*/
1440 PDM_SNPF(out_len, used, output + used, out_len - used,
1441 "print {0: all(Hex)}\n");
1442 PDM_SNPF(out_len, used, output + used, out_len - used,
1443 "print {1: partial} {0:hex 1:dec 2: s-dec} {bit_L} {bit_H}\n\n");
1444
1445 /*Fast Trigger*/
1446 PDM_SNPF(out_len, used, output + used, out_len - used,
1447 "fast {0: CCA trig & AGC Dbg Port}\n");
1448 PDM_SNPF(out_len, used, output + used, out_len - used,
1449 "fast {1: CCA trig & EVM Dbg Port}\n");
1450 PDM_SNPF(out_len, used, output + used, out_len - used,
1451 "fast {2: CCA trig & SNR Dbg Port}\n");
1452 PDM_SNPF(out_len, used, output + used, out_len - used,
1453 "fast {3: CCA trig & CFO Dbg Port}\n");
1454 PDM_SNPF(out_len, used, output + used, out_len - used,
1455 "fast {4: CCA trig & ADC output Dbg Port}\n");
1456 PDM_SNPF(out_len, used, output + used, out_len - used,
1457 "fast {10: EVM>=-X dB, 11: EVM<=-X dB} {X=2/4/8/16/32/64} {0:Lgcy, 1:HT}\n");
1458 PDM_SNPF(out_len, used, output + used, out_len - used,
1459 "fast {12: EVM=-X dB} {X} {0:Lgcy, 1:HT}\n");
1460 PDM_SNPF(out_len, used, output + used, out_len - used,
1461 "fast {20: RX-rate-idx=X} {X}\n");
1462
1463 PDM_SNPF(out_len, used, output + used, out_len - used,
1464 "=================================================\n");
1465 } else if ((strcmp(input[1], "print") == 0)) {
1466 phydm_la_buffer_print(dm, input, &used, output, &out_len);
1467 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
1468 } else if ((strcmp(input[1], "fast") == 0)) {
1469 phydm_la_cmd_fast_jgr3(dm, input, &used, output, &out_len);
1470
1471 } else if ((strcmp(input[1], "adv") == 0)) {
1472 phydm_la_bb_adv_cmd_jgr3(dm, input, &used, output, &out_len);
1473 #endif
1474 } else if ((strcmp(input[1], "set") == 0)) {
1475 PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
1476
1477 if (var1[1] == 1) {
1478 PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
1479 phydm_la_set_buff_mode(dm, (enum la_buff_mode)var1[2]);
1480 PDM_SNPF(out_len, used, output + used, out_len - used,
1481 "Buff_mode=(%d/2)\n", smp->la_buff_mode + 1);
1482 } else if (var1[1] == 2) {
1483 PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
1484 smp->en_fake_trig = (boolean)var1[2];
1485
1486 PDM_SNPF(out_len, used, output + used, out_len - used,
1487 "en_fake_trig=(%d)\n", smp->en_fake_trig);
1488 } else if (var1[1] == 3) {
1489 PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
1490 smp->is_la_print = (boolean)var1[2];
1491 PDM_SNPF(out_len, used, output + used, out_len - used,
1492 "Auto print=(%d)\n", smp->is_la_print);
1493 }
1494 } else if (var1[0] == 1) {
1495 PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
1496
1497 smp->la_trig_mode = (u8)var1[1];
1498
1499 if (smp->la_trig_mode == PHYDM_MAC_TRIG)
1500 PHYDM_SSCANF(input[3], DCMD_HEX, &var1[2]);
1501 else
1502 PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
1503 smp->la_trig_sig_sel = var1[2];
1504
1505 PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);
1506 PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var1[4]);
1507 PHYDM_SSCANF(input[6], DCMD_HEX, &var1[5]);
1508 PHYDM_SSCANF(input[7], DCMD_HEX, &var1[6]);
1509 PHYDM_SSCANF(input[8], DCMD_DECIMAL, &var1[7]);
1510 PHYDM_SSCANF(input[9], DCMD_DECIMAL, &var1[8]);
1511 PHYDM_SSCANF(input[10], DCMD_DECIMAL, &var1[9]);
1512
1513 smp->la_dma_type = (u8)var1[3];
1514 smp->la_trigger_time = var1[4]; /*unit: us*/
1515 smp->la_mac_mask_or_hdr_sel = var1[5];
1516 smp->la_dbg_port = var1[6];
1517 smp->la_trigger_edge = (u8)var1[7];
1518 smp->la_smp_rate = (u8)(var1[8] & 0x7);
1519 smp->la_count = var1[9];
1520
1521 pr_debug("echo lamode %d %d %d %d %d %d %x %d %d %d\n",
1522 var1[0], var1[1], var1[2], var1[3], var1[4],
1523 var1[5], var1[6], var1[7], var1[8], var1[9]);
1524 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1525 RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
1526 ("echo lamode %d %d %d %d %d %d %x %d %d %d\n",
1527 var1[0], var1[1], var1[2], var1[3],
1528 var1[4], var1[5], var1[6], var1[7],
1529 var1[8], var1[9]));
1530 #endif
1531
1532 PDM_SNPF(out_len, used, output + used, out_len - used,
1533 "a.En= ((1)), b.mode = ((%d)), c.Trig_Sel = ((0x%x)), d.Dma_type = ((%d))\n",
1534 smp->la_trig_mode, smp->la_trig_sig_sel,
1535 smp->la_dma_type);
1536 PDM_SNPF(out_len, used, output + used, out_len - used,
1537 "e.Trig_Time = ((%dus)), f.Dbg_head/mac_ref_mask = ((0x%x)), g.dbg_port = ((0x%x))\n",
1538 smp->la_trigger_time,
1539 smp->la_mac_mask_or_hdr_sel, smp->la_dbg_port);
1540 PDM_SNPF(out_len, used, output + used, out_len - used,
1541 "h.Trig_edge = ((%d)), i.smp rate = ((%d MHz)), j.Cap_num = ((%d))\n",
1542 smp->la_trigger_edge, (80 >> smp->la_smp_rate),
1543 smp->la_count);
1544
1545 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
1546 PDM_SNPF(out_len, used, output + used, out_len - used,
1547 "k.en_new_bbtrigger = ((%d))\n",
1548 smp->adv_trig_table.la_adv_bbtrigger_en);
1549 #endif
1550
1551 phydm_la_set(dm);
1552 } else {
1553 phydm_la_stop(dm);
1554 PDM_SNPF(out_len, used, output + used, out_len - used,
1555 "Disable LA mode\n");
1556 }
1557
1558 *_used = used;
1559 *_out_len = out_len;
1560 }
1561
phydm_la_stop(void * dm_void)1562 void phydm_la_stop(void *dm_void)
1563 {
1564 struct dm_struct *dm = (struct dm_struct *)dm_void;
1565 struct rt_adcsmp *smp = &dm->adcsmp;
1566
1567 smp->adc_smp_state = ADCSMP_STATE_IDLE;
1568 }
1569
phydm_la_init(void * dm_void)1570 void phydm_la_init(void *dm_void)
1571 {
1572 struct dm_struct *dm = (struct dm_struct *)dm_void;
1573 struct rt_adcsmp *smp = &dm->adcsmp;
1574 struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
1575
1576 if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE))
1577 return;
1578
1579 smp->adc_smp_state = ADCSMP_STATE_IDLE;
1580 smp->is_la_print = true;
1581 smp->en_fake_trig = false;
1582 smp->txff_page = 0xffffffff;
1583 phydm_la_set_buff_mode(dm, ADCSMP_BUFF_HALF);
1584
1585 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
1586 phydm_la_bb_adv_reset_jgr3(dm);
1587 #endif
1588 }
1589
adc_smp_de_init(void * dm_void)1590 void adc_smp_de_init(void *dm_void)
1591 {
1592 struct dm_struct *dm = (struct dm_struct *)dm_void;
1593
1594 if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE))
1595 return;
1596
1597 phydm_la_stop(dm);
1598 phydm_la_buffer_release(dm);
1599 }
1600
1601 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
adc_smp_work_item_callback(void * context)1602 void adc_smp_work_item_callback(void *context)
1603 {
1604 void *adapter = (void *)context;
1605 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
1606 struct dm_struct *dm = &hal_data->DM_OutSrc;
1607 struct rt_adcsmp *smp = &dm->adcsmp;
1608
1609 pr_debug("[WorkItem Call back] LA_State=(%d)\n", smp->adc_smp_state);
1610 phydm_la_adc_smp_start(dm);
1611 }
1612 #endif
1613 #endif /*@endif PHYDM_LA_MODE_SUPPORT*/
1614