1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #include "mp_precomp.h"
27 #include "phydm_precomp.h"
28
29 #if (PHYDM_LA_MODE_SUPPORT)
30
31 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
32 #if (RTL8197F_SUPPORT || RTL8822B_SUPPORT || RTL8192F_SUPPORT)
33 #include "rtl8197f/Hal8197FPhyReg.h"
34 #include "WlanHAL/HalMac88XX/halmac_reg2.h"
35 #else
36 #include "WlanHAL/HalHeader/HalComReg.h"
37 #endif
38 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
39 #if WPP_SOFTWARE_TRACE
40 #include "phydm_adc_sampling.tmh"
41 #endif
42 #endif
43
44 #if RTL8814B_SUPPORT
phydm_la_finish_addr_recover_8814B(void * dm_void,u32 * finish_addr)45 boolean phydm_la_finish_addr_recover_8814B(void *dm_void, u32 *finish_addr)
46 {
47 struct dm_struct *dm = (struct dm_struct *)dm_void;
48 struct rt_adcsmp *smp = &dm->adcsmp;
49 boolean recover_success;
50
51 if (dm->support_ic_type != ODM_RTL8814B)
52 return false;
53
54 if (smp->la_buff_mode == ADCSMP_BUFF_HALF) {
55 if (*finish_addr < 0x4000) /*0~0x4000*/
56 *finish_addr += 0x8000;
57
58 recover_success = true;
59 } else {
60 if (*finish_addr >= 0x4000 && *finish_addr < 0x8000)
61 recover_success = true;
62 else
63 recover_success = false;
64 }
65 pr_debug("[8814B] recover_success=(%d)\n", recover_success);
66
67 return recover_success;
68 }
69 #endif
70
71 #if RTL8198F_SUPPORT
phydm_la_pre_run(void * dm_void)72 void phydm_la_pre_run(void *dm_void)
73 {
74 struct dm_struct *dm = (struct dm_struct *)dm_void;
75 struct rt_adcsmp *smp = &dm->adcsmp;
76 struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
77 u8 i = 0;
78 u8 tmp = 0;
79 u8 target_polling_bit = BIT(1);
80
81 if (!(dm->support_ic_type & ODM_RTL8198F))
82 return;
83
84 if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG)
85 return;
86
87 /*pre run */
88 /*force to bb trigger*/
89 odm_set_mac_reg(dm, R_0x7c0, BIT(3), 0);
90 /*dma_trig_and(AND1) output 1*/
91 odm_set_bb_reg(dm, R_0x1ce4, 0xf0000000, 0x0);
92 /*r_dma_trigger_AND1_inv = 1*/
93 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 1); /*@AND 1 val*/
94 /* polling bit for BB ADC mode */
95 odm_set_mac_reg(dm, R_0x7c0, BIT(1), 1);
96
97 pr_debug("buf[end:start]=(0x%x~0x%x)\n", buf->end_pos, buf->start_pos);
98
99 do {
100 tmp = odm_read_1byte(dm, R_0x7c0);
101 if ((tmp & target_polling_bit) == false) {
102 pr_debug("LA pre-run fail.\n");
103 phydm_la_stop(dm);
104 phydm_release_bb_dbg_port(dm);
105 } else {
106 ODM_delay_ms(100);
107 pr_debug("LA pre-run while_cnt = %d.\n", i);
108 i++;
109 }
110 } while (i < 3);
111
112 /*r_dma_trigger_AND1_inv = 0*/
113 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 0); /*@AND 1 val*/
114
115 if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG)
116 odm_set_mac_reg(dm, R_0x7c0, BIT(3), 1);
117 }
118 #endif
119
120 #if (RTL8821C_SUPPORT || RTL8195B_SUPPORT)
121 void
phydm_la_clk_en(void * dm_void,boolean enable)122 phydm_la_clk_en(void *dm_void, boolean enable)
123 {
124 struct dm_struct *dm = (struct dm_struct *)dm_void;
125 u8 val = (enable) ? 1 : 0;
126
127 if (!(dm->support_ic_type & (ODM_RTL8195B | ODM_RTL8821C)))
128 return;
129
130 if (dm->support_ic_type == ODM_RTL8821C &&
131 dm->cut_version == ODM_CUT_A)
132 return;
133
134 odm_set_bb_reg(dm, R_0x95c, BIT(23), val);
135 }
136 #endif
137
138 #if (RTL8723F_SUPPORT)
139 void
phydm_la_mac_clk_en(void * dm_void,boolean enable)140 phydm_la_mac_clk_en(void *dm_void, boolean enable)
141 {
142 struct dm_struct *dm = (struct dm_struct *)dm_void;
143 u8 val = (enable) ? 1 : 0;
144
145 if (!(dm->support_ic_type & ODM_RTL8723F))
146 return;
147
148 odm_set_mac_reg(dm, R_0x1008, BIT(1), val);
149 /*Set IRAM2/3*/
150 odm_set_mac_reg(dm, R_0x1000, 0xc0, 0x0);
151 odm_set_mac_reg(dm, R_0x1000, 0x3000, 0x3);
152 }
153 #endif
154
155 #if (RTL8197F_SUPPORT)
156 void
phydm_la_stop_dma_8197f(void * dm_void,enum phydm_backup_type opt)157 phydm_la_stop_dma_8197f(void *dm_void, enum phydm_backup_type opt)
158 {
159 struct dm_struct *dm = (struct dm_struct *)dm_void;
160 struct rt_adcsmp *smp = &dm->adcsmp;
161
162 if (dm->support_ic_type != ODM_RTL8197F)
163 return;
164
165 if (opt == PHYDM_BACKUP) {
166 /*Stop DMA*/
167 smp->backup_dma = odm_get_mac_reg(dm, R_0x300, 0xffff);
168 odm_set_mac_reg(dm, R_0x300, 0x7fff, 0x7fff);
169 } else { /*restore*/
170 /*Resume DMA*/
171 odm_set_mac_reg(dm, R_0x300, 0x7fff, smp->backup_dma);
172 }
173 }
174 #endif
175
176 #ifdef PHYDM_COMPILE_LA_STORE_IN_IMEM
177 void
phydm_la_mv_data_2_tx_buffer(void * dm_void)178 phydm_la_mv_data_2_tx_buffer(void *dm_void)
179 {
180 struct dm_struct *dm = (struct dm_struct *)dm_void;
181 struct rt_adcsmp *smp = &dm->adcsmp;
182 struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
183
184 if (!(dm->support_ic_type & PHYDM_LA_STORE_IN_IMEM_IC))
185 return;
186
187 pr_debug("GetTxPktBuf from iMEM\n");
188 odm_set_mac_reg(dm, R_0x7c0, BIT(0), 0x0); /*Disable LA mode HW block*/
189
190 /* 98F LA memory loccation is separate from normal
191 * driver use, DMA is no longer required to stop
192 */
193 #if (RTL8197F_SUPPORT)
194 phydm_la_stop_dma_8197f(dm, PHYDM_BACKUP);
195 #endif
196
197 /* @move LA mode content from IMEM to TxPktBuffer
198 * Source : OCPBASE_IMEM 0x00000000
199 * Destination : OCPBASE_TXBUF 0x18780000
200 * Length : 64K
201 */
202 GET_HAL_INTERFACE(dm->priv)->init_ddma_handler(dm->priv,
203 OCPBASE_IMEM,
204 OCPBASE_TXBUF
205 + buf->start_pos,
206 0x10000);
207 }
208 #endif
209
210
211 #if(RTL8723F_SUPPORT)
212 void
phydm_la_mv_data_2_tx_buffer_rtl8723f(void * dm_void,u32 source,u32 dest,u32 length)213 phydm_la_mv_data_2_tx_buffer_rtl8723f(void *dm_void, u32 source, u32 dest, u32 length)
214 {
215 struct dm_struct *dm = (struct dm_struct *)dm_void;
216 struct rt_adcsmp *smp = &dm->adcsmp;
217 struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
218 //u32 ch0ctrl = (BIT(29)|BIT(31));
219 u32 ch0ctrl = BIT(31);
220 u32 cnt=25000;
221
222 pr_debug("GetTxPktBuf from iMEM\n");
223 /*Disable LA mode HW block*/
224 odm_set_mac_reg(dm, R_0x7c0, BIT(0), 0x0);
225
226 /* @move LA mode content from IMEM to TxPktBuffer
227 * Source : OCPBASE_IMEM 0x14040000
228 * Destination : OCPBASE_TXBUF 0x18780000
229 * Length : 32K
230 */
231 /*
232 OCPBASE_IMEM = 0x18600000;
233 OCPBASE_TXBUF = 0x18780000;
234 GET_HAL_INTERFACE(dm->priv)->init_ddma_handler(dm->priv,
235 OCPBASE_IMEM,
236 OCPBASE_TXBUF
237 + buf->start_pos,
238 0x8000);
239 */
240
241 // TODO: Replace all register define & bit define
242
243
244 //check if ddma ch0 is idle
245 while(odm_get_mac_reg(dm, R_0x1208 , BIT(31))){
246 ODM_delay_ms(10);
247 cnt--;
248 if(cnt==0){
249 pr_debug("1 InitDDMA88XX polling fail \n");
250 return;
251 }
252 }
253
254 ch0ctrl |= length & 0x3FFFF;
255
256 //check if chksum continuous
257 //ch0ctrl |= BIT(24);
258
259 odm_set_mac_reg(dm, R_0x1200, MASKDWORD, source); /*0x1200[31:0]:Source Address*/
260 odm_set_mac_reg(dm, R_0x1204, MASKDWORD, dest); /*0x1204[31:0]:Destination Address*/
261 odm_set_mac_reg(dm, R_0x1208, MASKDWORD, ch0ctrl); /*0x1208[17:0]:DMA Length*/
262 //check if ddma ch0 is idle
263 while(odm_get_mac_reg(dm, R_0x1208 , BIT(31))){
264 ODM_delay_ms(10);
265 cnt--;
266 if(cnt==0){
267 pr_debug("2 InitDDMA88XX polling fail \n");
268 return ;
269 }
270 }
271 }
272 #endif
273
274 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
275
phydm_la_bb_adv_reset_jgr3(void * dm_void)276 void phydm_la_bb_adv_reset_jgr3(void *dm_void)
277 {
278 struct dm_struct *dm = (struct dm_struct *)dm_void;
279 struct rt_adcsmp *smp = &dm->adcsmp;
280 struct la_adv_trig *adv = &smp->adv_trig_table;
281
282 odm_memory_set(dm, adv, 0, sizeof(struct la_adv_trig));
283
284 }
285
phydm_la_bb_adv_trig_setting_jgr3(void * dm_void)286 void phydm_la_bb_adv_trig_setting_jgr3(void *dm_void)
287 {
288 struct dm_struct *dm = (struct dm_struct *)dm_void;
289 struct rt_adcsmp *smp = &dm->adcsmp;
290 struct la_adv_trig *adv = &smp->adv_trig_table;
291
292 pr_debug(" *ADV BB-trig = %d\n", adv->la_adv_bbtrigger_en);
293
294 if (!adv->la_adv_bbtrigger_en) { /*normal LA mode & back to default*/
295 /*@AND0*/
296 odm_set_bb_reg(dm, R_0x1ce4, BIT(27), 0);
297
298 /*@AND1*/
299 odm_set_bb_reg(dm, R_0x1ce4, MASKH4BITS, 0);
300 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), 0); /*@AND 1 inv*/
301 /*@AND2*/
302 odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, 0);
303 odm_set_bb_reg(dm, R_0x1ce8, BIT(15), 0); /*@AND 2 inv*/
304 /*@AND3*/
305 odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, 0);
306 odm_set_bb_reg(dm, R_0x1ce8, BIT(25), 0); /*@AND 3 inv*/
307 /*@AND4*/
308 odm_set_bb_reg(dm, R_0x1cf0, MASKDWORD, 0); /*@AND 4 mask en*/
309 odm_set_bb_reg(dm, R_0x1ce8, BIT(26), 0); /*@AND 4 inv*/
310 } else {
311 /*@AND0 */
312 /*path 1 default: enable ori. BB trigger*/
313 odm_set_bb_reg(dm, R_0x1ce4, BIT(27),
314 (adv->la_ori_bb_dis ? 1 : 0));
315
316 /* @AND1 */
317 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), adv->la_and1_inv);
318 odm_set_bb_reg(dm, R_0x1ce4, MASKH4BITS, adv->la_and1_sel);
319 odm_set_bb_reg(dm, R_0x1ce8, 0x1f, adv->la_and1_val);
320
321 /*@AND2 */
322 odm_set_bb_reg(dm, R_0x1ce8, BIT(15), adv->la_and2_inv);
323 odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, adv->la_and2_sel);
324 odm_set_bb_reg(dm, R_0x1ce8, 0x7c00, adv->la_and2_val);
325
326 /*@AND3 */
327 odm_set_bb_reg(dm, R_0x1ce8, BIT(25), adv->la_and3_inv);
328 odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, adv->la_and3_sel);
329 odm_set_bb_reg(dm, R_0x1ce8, 0x1f00000, adv->la_and3_val);
330
331 /*@AND4 */
332 odm_set_bb_reg(dm, R_0x1ce8, BIT(26), adv->la_and4_inv);
333 odm_set_bb_reg(dm, R_0x1cf0, MASKDWORD, adv->la_and4_mask);
334 odm_set_bb_reg(dm, R_0x1cec, MASKDWORD, adv->la_and4_bitmap);
335 }
336 }
337
phydm_la_bb_adv_cmd_show_jgr3(void * dm_void,u32 * _used,char * output,u32 * _out_len)338 void phydm_la_bb_adv_cmd_show_jgr3(void *dm_void, u32 *_used,
339 char *output, u32 *_out_len)
340 {
341 struct dm_struct *dm = (struct dm_struct *)dm_void;
342 struct rt_adcsmp *smp = &dm->adcsmp;
343 struct la_adv_trig *adv = &smp->adv_trig_table;
344
345 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
346 " *And0 Disable=%d\n", adv->la_ori_bb_dis);
347 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
348 " *And1{sel,val,inv}={0x%x,0x%x,%d}\n *And2{sel,val,inv}={0x%x,0x%x,%d}\n *And3{sel,val,inv}={0x%x,0x%x,%d}\n",
349 adv->la_and1_sel, adv->la_and1_val, adv->la_and1_inv,
350 adv->la_and2_sel, adv->la_and2_val, adv->la_and2_inv,
351 adv->la_and3_sel, adv->la_and3_val, adv->la_and3_inv);
352 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
353 " *And4{mask,bitmap,inv}={0x%x,0x%x,%d}\n",
354 adv->la_and4_mask, adv->la_and4_bitmap, adv->la_and4_inv);
355 }
356
phydm_la_bb_adv_cmd_jgr3(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)357 void phydm_la_bb_adv_cmd_jgr3(void *dm_void, char input[][16], u32 *_used,
358 char *output, u32 *_out_len)
359 {
360 struct dm_struct *dm = (struct dm_struct *)dm_void;
361 struct rt_adcsmp *smp = &dm->adcsmp;
362 struct la_adv_trig *adv = &smp->adv_trig_table;
363 u32 var1[10] = {0};
364 u32 adv_trig_en;
365
366 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
367 return;
368
369 if ((strcmp(input[2], "show") == 0)) {
370 phydm_la_bb_adv_cmd_show_jgr3(dm, _used, output, _out_len);
371 return;
372 }
373
374 PHYDM_SSCANF(input[2], DCMD_HEX, &var1[0]);
375 PHYDM_SSCANF(input[3], DCMD_HEX, &var1[1]);
376 PHYDM_SSCANF(input[4], DCMD_HEX, &var1[2]);
377 PHYDM_SSCANF(input[5], DCMD_HEX, &var1[3]);
378 PHYDM_SSCANF(input[6], DCMD_HEX, &var1[4]);
379
380 adv_trig_en = var1[0];
381
382 if (adv_trig_en != 1) {
383 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
384 "Back to Ori-BB-trig\n");
385 phydm_la_bb_adv_reset_jgr3(dm);
386 return;
387 }
388
389 adv->la_adv_bbtrigger_en = true;
390
391 if (var1[1] == 0) {
392 adv->la_ori_bb_dis = (boolean)var1[2];
393 } else if (var1[1] == 1) {
394 adv->la_and1_sel = (u8)var1[2];
395 adv->la_and1_val = (u8)var1[3];
396 adv->la_and1_inv = (boolean)var1[4];
397 } else if (var1[1] == 2) {
398 adv->la_and2_sel = (u8)var1[2];
399 adv->la_and2_val = (u8)var1[3];
400 adv->la_and2_inv = (boolean)var1[4];
401 } else if (var1[1] == 3) {
402 adv->la_and3_sel = (u8)var1[2];
403 adv->la_and3_val = (u8)var1[3];
404 adv->la_and2_inv = (boolean)var1[4];
405 } else if (var1[1] == 4) {
406 adv->la_and4_mask = var1[2];
407 adv->la_and4_bitmap = var1[3];
408 adv->la_and4_inv = (boolean)var1[4];
409 }
410
411 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
412 "[Adv_trig_en=%d]\n\n", adv_trig_en);
413
414 phydm_la_bb_adv_cmd_show_jgr3(dm, _used, output, _out_len);
415 }
416
phydm_la_cmd_fast_jgr3(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)417 void phydm_la_cmd_fast_jgr3(void *dm_void, char input[][16], u32 *_used,
418 char *output, u32 *_out_len)
419 {
420 struct dm_struct *dm = (struct dm_struct *)dm_void;
421 struct rt_adcsmp *smp = &dm->adcsmp;
422 struct la_adv_trig *adv = &smp->adv_trig_table;
423 enum auto_detection_state ad_mode;
424 const u8 ofdm_codeword[8] = {0xb, 0xf, 0xa, 0xe, 0x9, 0xd, 0x8, 0xc};
425 u32 codeword;
426 u8 rate_idx;
427 u32 trig_time_cca = 0;
428 s32 val_sign32_tmp = 0;
429 u32 var[10] = {0};
430 u8 bw = *dm->band_width;
431
432 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) {
433 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
434 "Only Support for JGR-3 ICs\n");
435 return;
436 }
437
438 if (bw > 2) {
439 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
440 "Not Support for BW > %dM\n", 20 << bw);
441 return;
442 }
443
444 PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var[0]);
445 PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var[1]);
446 PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var[2]);
447
448 trig_time_cca = ((smp->smp_number_max >> (bw + 1)) / 10)
449 - (2 << (2 - bw)) - (2 - bw);
450
451 if (var[0] < 10) {
452 /*=== [Type: 0 ~ 10] : CCA P-edge trigger ==========================*/
453 /*--- Basic Trigger Setting --------------------------------*/
454 smp->la_trig_mode = 1;
455 smp->la_trig_sig_sel = 2;
456 smp->la_trigger_time = trig_time_cca;
457 smp->la_mac_mask_or_hdr_sel = 0;
458 smp->la_trigger_edge = 0;
459 smp->la_smp_rate = 2 - bw;
460 smp->la_count = 0;
461 if (var[0] == 0) { /*AGC*/
462 smp->la_dma_type = 5;
463 smp->la_dbg_port = 0x870;
464 } else if (var[0] == 1) { /*EVM*/
465 smp->la_dma_type = 4;
466 smp->la_dbg_port = 0x392;
467 } else if (var[0] == 2) { /*SNR*/
468 smp->la_dma_type = 4;
469 if (var[1] == 0)
470 smp->la_dbg_port = 0x89e;
471 else
472 smp->la_dbg_port = 0xa9e;
473 } else if (var[0] == 3) { /*CFO*/
474 smp->la_dma_type = 4;
475 if (var[1] == 0)
476 smp->la_dbg_port = 0x88c;
477 else
478 smp->la_dbg_port = 0xa8c;
479 } else if (var[0] == 4) { /*ADC*/
480 if (var[1] == 0) {
481 smp->la_dma_type = 0;
482 smp->la_dbg_port = 0x880;
483 } else {
484 smp->la_dma_type = 1;
485 smp->la_dbg_port = 0xa80;
486 }
487 }
488 /*--- Adv-Trigger Setting------------------------------------*/
489 adv->la_adv_bbtrigger_en = false;
490 } else if (var[0] < 20) {
491 /*=== [Type: 10 ~ 19]: RX-EVM Trigger ===============================*/
492 /*--- Basic Trigger Setting ---------------------------------*/
493 smp->la_trig_mode = 0;
494 smp->la_trig_sig_sel = 0;
495 smp->la_mac_mask_or_hdr_sel = 0;
496 smp->la_trigger_edge = 0;
497 smp->la_smp_rate = 2 - bw;
498 smp->la_count = 0;
499 smp->la_dma_type = 4;
500 smp->la_dbg_port = 0x392;
501
502 /*--- Adv-Trigger Setting -----------------------------------*/
503 phydm_la_bb_adv_reset_jgr3(dm);
504 adv->la_adv_bbtrigger_en = true;
505
506 /*And[0]*/
507 adv->la_ori_bb_dis = true;
508
509 /*And[1]*/
510 adv->la_and1_inv = 0;
511 adv->la_and1_sel = 4; /*RX-state*/
512 if (var[2] == 0) {
513 /*L-preamble 8+8+4 = 20*/
514 smp->la_trigger_time = trig_time_cca - 20;
515 /*Legacy Data*/
516 adv->la_and1_val = 5;
517 } else if (var[2] == 1) {
518 /*HT-preamble (8+8+4) + (8+4+4*Nrx) = 32 + Nrx * 4*/
519 smp->la_trigger_time = trig_time_cca - 32 -
520 (dm->num_rf_path * 4);
521 /*HT Data*/
522 adv->la_and1_val = 18;
523 } else {
524 /*VHT-preamble (8+8+4) + (8+4+4*Nrx) +4 = 36 + Nrx * 4*/
525 smp->la_trigger_time = trig_time_cca - 36 -
526 (dm->num_rf_path * 4);
527 /*VHT Data*/
528 adv->la_and1_val = 18;
529 }
530
531 /*And[2]*/
532 adv->la_and2_inv = 0;
533 adv->la_and2_sel = 0; /*Disable*/
534
535 /*And[3]*/
536 adv->la_and2_inv = 0;
537 adv->la_and3_sel = 0; /*Disable*/
538
539 /*And[4]*/
540 adv->la_and4_inv = 0;
541
542 if (var[0] == 11) {
543 /*[>= -X dB]*/
544 if (var[1] == 2) {
545 adv->la_and4_bitmap = 0;
546 adv->la_and4_mask = 0x1;
547 } else if (var[1] == 4) {
548 adv->la_and4_bitmap = 0;
549 adv->la_and4_mask = 0x3;
550 } else if (var[1] == 8) {
551 adv->la_and4_bitmap = 0;
552 adv->la_and4_mask = 0x7;
553 } else if (var[1] == 16) {
554 adv->la_and4_bitmap = 0;
555 adv->la_and4_mask = 0xf;
556 } else if (var[1] == 32) {
557 adv->la_and4_bitmap = 0;
558 adv->la_and4_mask = 0x1f;
559 } else if (var[1] == 64) {
560 adv->la_and4_bitmap = 0;
561 adv->la_and4_mask = 0x3f;
562 } else {
563 PDM_SNPF(*_out_len, *_used, output + *_used,
564 *_out_len - *_used,
565 "Not Support >= -%d dB\n", var[1]);
566 return;
567 }
568 } else if (var[0] == 10) {
569 /*[<= -X dB]*/
570 if (var[1] == 2) {
571 adv->la_and4_bitmap = 0x7e;
572 adv->la_and4_mask = 0x7e;
573 } else if (var[1] == 4) {
574 adv->la_and4_bitmap = 0x7c;
575 adv->la_and4_mask = 0x7c;
576 } else if (var[1] == 8) {
577 adv->la_and4_bitmap = 0x78;
578 adv->la_and4_mask = 0x78;
579 } else if (var[1] == 16) {
580 adv->la_and4_bitmap = 0x70;
581 adv->la_and4_mask = 0x70;
582 } else if (var[1] == 32) {
583 adv->la_and4_bitmap = 0x60;
584 adv->la_and4_mask = 0x60;
585 } else if (var[1] == 64) {
586 adv->la_and4_bitmap = 0x40;
587 adv->la_and4_mask = 0x40;
588 } else {
589 PDM_SNPF(*_out_len, *_used, output + *_used,
590 *_out_len - *_used,
591 "Not Support <= -%d dB\n", var[1]);
592 return;
593 }
594 } else if (var[0] == 12) {
595 /*[= -X dB]*/
596 val_sign32_tmp = 0 - (s32)var[1];
597 adv->la_and4_bitmap = (u32)(val_sign32_tmp & 0x7f);
598 adv->la_and4_mask = 0x7f;
599 }
600 } else if (var[0] < 30) {
601 /*=== [Type: 20 ~ 29]: RX-Rate Trigger ==============================*/
602 /*--- Basic Trigger Setting ---------------------------------*/
603 smp->la_trig_mode = 0;
604 smp->la_trig_sig_sel = 0;
605 smp->la_mac_mask_or_hdr_sel = 0;
606 smp->la_trigger_edge = 0;
607 smp->la_smp_rate = 2 - bw;
608 smp->la_count = 0;
609 smp->la_dma_type = 4;
610
611 rate_idx = (u8)var[1];
612
613 /*--- Adv-Trigger Setting -----------------------------------*/
614 phydm_la_bb_adv_reset_jgr3(dm);
615 adv->la_adv_bbtrigger_en = true;
616
617 /*And[0]*/
618 adv->la_ori_bb_dis = true;
619
620 /*And[1]*/
621 adv->la_and1_inv = 0;
622 adv->la_and1_sel = 4; /*RX-state*/
623
624 if (rate_idx <= ODM_RATE54M && rate_idx >= ODM_RATE6M) {
625 ad_mode = AD_LEGACY_MODE;
626 codeword = (u32)ofdm_codeword[rate_idx - ODM_RATE6M];
627 smp->la_dbg_port = 0x3a9;
628 /*L-preamble 8+8 = 16*/
629 smp->la_trigger_time = trig_time_cca - 20;
630 /*Legacy Data*/
631 adv->la_and1_val = 5;
632 } else if (rate_idx <= ODM_RATEMCS31) {
633 ad_mode = AD_HT_MODE;
634 codeword = (u32)(rate_idx - ODM_RATEMCS0);
635 smp->la_dbg_port = 0x3aa;
636 /*HT-preamble (8+8+4) + (8+4+4*Nrx) = 32 + Nrx * 4*/
637 smp->la_trigger_time = trig_time_cca - 32 -
638 (dm->num_rf_path * 4);
639 /*HT,VHT Data*/
640 adv->la_and1_val = 18;
641 } else if (rate_idx <= ODM_RATEVHTSS4MCS9) {
642 ad_mode = AD_VHT_MODE;
643 codeword = (u32)phydm_rate_order_compute(dm, rate_idx);
644 codeword--;
645 smp->la_dbg_port = 0x3ab;
646 /*VHT-preamble (8+8+4) + (8+4+4*Nrx) = 36 + Nrx * 4*/
647 smp->la_trigger_time = trig_time_cca - 36 -
648 (dm->num_rf_path * 4);
649 /*HT,VHT Data*/
650 adv->la_and1_val = 18;
651 } else {
652 PDM_SNPF(*_out_len, *_used, output + *_used,
653 *_out_len - *_used,
654 "Not Support\n");
655 return;
656 }
657
658 /*And[2]*/
659 adv->la_and2_inv = 0;
660 adv->la_and2_sel = 0; /*Disable*/
661
662 /*And[3]*/
663 adv->la_and2_inv = 0;
664 adv->la_and3_sel = 0; /*Disable*/
665
666 /*And[4]*/
667 adv->la_and4_inv = 0;
668
669 if (var[0] == 20) {
670 if (ad_mode == AD_LEGACY_MODE) {
671 adv->la_and4_bitmap = codeword;
672 adv->la_and4_mask = 0x3000000f;
673 } else if (ad_mode == AD_HT_MODE) {
674 adv->la_and4_bitmap = (2 << 28) | codeword;
675 adv->la_and4_mask = 0x3000003f;
676 } else { /* AD_VHT_MODE*/
677 adv->la_and4_bitmap = (1 << 28) |
678 (codeword << 4);
679 adv->la_and4_mask = 0x300000f0;
680 }
681 } else {
682 PDM_SNPF(*_out_len, *_used, output + *_used,
683 *_out_len - *_used,
684 "Not Support\n");
685 return;
686 }
687 } else {
688 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
689 "Not Support\n");
690 return;
691 }
692 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
693 "[Basic-Trigger]\n");
694 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
695 " *echo lamode 1 %d %d %d %d %d %x %d %d %d\n\n",
696 smp->la_trig_mode, smp->la_trig_sig_sel, smp->la_dma_type,
697 smp->la_trigger_time, smp->la_mac_mask_or_hdr_sel,
698 smp->la_dbg_port, smp->la_trigger_edge, smp->la_smp_rate,
699 smp->la_count);
700 pr_debug("echo lamode 1 %d %d %d %d %d %x %d %d %d\n\n",
701 smp->la_trig_mode, smp->la_trig_sig_sel, smp->la_dma_type,
702 smp->la_trigger_time, smp->la_mac_mask_or_hdr_sel,
703 smp->la_dbg_port, smp->la_trigger_edge, smp->la_smp_rate,
704 smp->la_count);
705
706 if (adv->la_adv_bbtrigger_en) {
707 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
708 "[Adv-Trigger]\n");
709 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
710 " *And0 Disable=%d\n", adv->la_ori_bb_dis);
711 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
712 " *And1{sel,val,inv}={0x%x,0x%x,%d}\n *And2{sel,val,inv}={0x%x,0x%x,%d}\n *And3{sel,val,inv}={0x%x,0x%x,%d}\n",
713 adv->la_and1_sel, adv->la_and1_val, adv->la_and1_inv,
714 adv->la_and2_sel, adv->la_and2_val, adv->la_and2_inv,
715 adv->la_and3_sel, adv->la_and3_val, adv->la_and3_inv);
716 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
717 " *And4{mask,bitmap,inv}={0x%x,0x%x,%d}\n",
718 adv->la_and4_mask, adv->la_and4_bitmap,
719 adv->la_and4_inv);
720 }
721 phydm_la_set(dm);
722 }
723
724 #endif
725
726 void
phydm_la_buffer_print(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)727 phydm_la_buffer_print(void *dm_void, char input[][16], u32 *_used,
728 char *output, u32 *_out_len)
729 {
730 struct dm_struct *dm = (struct dm_struct *)dm_void;
731 struct rt_adcsmp *smp = &dm->adcsmp;
732 struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
733 u64 la_pattern_msb, la_pattern_lsb;
734 u64 la_pattern, la_pattern_part;
735 s64 tmp_s64;
736 u64 mask = 0xffffffff;
737 u8 mask_length = 0;
738 u32 i;
739 u32 idx;
740 u32 var[10] = {0};
741
742 if (!buf->octet || buf->length == 0 || buf->length < smp->smp_number)
743 return;
744
745 PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var[0]);
746 PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var[1]);
747 PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var[2]);
748 PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var[3]);
749
750 pr_debug("echo lamode 1 %d %d %d %d %d %x %d %d %d\n\n",
751 smp->la_trig_mode, smp->la_trig_sig_sel, smp->la_dma_type,
752 smp->la_trigger_time, smp->la_mac_mask_or_hdr_sel,
753 smp->la_dbg_port, smp->la_trigger_edge, smp->la_smp_rate,
754 smp->la_count);
755 pr_debug("[LA Data Dump] smp_number = %d\n", smp->smp_number);
756 pr_debug("Dump_Start\n");
757
758 if (var[0] == 0) {
759 for (i = 0; i < smp->smp_number; i++) {
760 idx = i << 1;
761 pr_debug("%08x%08x\n", buf->octet[idx],
762 buf->octet[idx + 1]);
763 }
764 } else if (var[0] == 1) {
765 /*------------------------*/
766 if (var[1] == 0)
767 pr_debug("[Hex]\n");
768 else if (var[1] == 1)
769 pr_debug("[Dec unsigned]\n");
770 else if (var[1] == 2)
771 pr_debug("[Dec signed]\n");
772
773 pr_debug("BIT[%d:%d]\n", var[3], var[2]);
774
775 if (var[2] > var[3]) {
776 pr_debug("[Warning] BIT_L > BIT_H\n");
777 return;
778 }
779
780 mask_length = (u8)(var[3] - var[2] + 1);
781 mask = phydm_gen_bitmask(mask_length) << var[2];
782 /*------------------------*/
783 for (i = 0; i < smp->smp_number; i++) {
784 idx = i << 1;
785 la_pattern_msb = (u64)buf->octet[idx];
786 la_pattern_lsb = (u64)buf->octet[idx + 1];
787 la_pattern = (la_pattern_msb << 32) | la_pattern_lsb;
788 la_pattern_part = (la_pattern & mask) >> var[2];
789
790 if (var[1] == 0) {
791 pr_debug("0x%llx\n", la_pattern_part);
792 } else if (var[1] == 1) {
793 pr_debug("%llu\n", la_pattern_part);
794 } else if (var[1] == 2) {
795 tmp_s64 = phydm_cnvrt_2_sign_64(la_pattern_part,
796 mask_length);
797 pr_debug("%lld\n", tmp_s64);
798 }
799 }
800 }
801 pr_debug("Dump_End\n\n");
802 }
803
804 void
phydm_la_buffer_release(void * dm_void)805 phydm_la_buffer_release(void *dm_void)
806 {
807 struct dm_struct *dm = (struct dm_struct *)dm_void;
808 struct rt_adcsmp *smp = &dm->adcsmp;
809 struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
810
811 if (buf->length != 0x0) {
812 odm_free_memory(dm, buf->octet, buf->length);
813 buf->length = 0x0;
814 }
815 }
816
817 boolean
phydm_la_buffer_allocate(void * dm_void)818 phydm_la_buffer_allocate(void *dm_void)
819 {
820 struct dm_struct *dm = (struct dm_struct *)dm_void;
821 struct rt_adcsmp *smp = &dm->adcsmp;
822 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
823 void *adapter = dm->adapter;
824 #endif
825 struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
826 boolean ret = true;
827
828 pr_debug("[LA mode BufferAllocate]\n");
829
830 if (buf->length == 0) {
831 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
832 if (PlatformAllocateMemoryWithZero(adapter, (void **)&
833 buf->octet,
834 buf->buffer_size) !=
835 RT_STATUS_SUCCESS)
836 ret = false;
837 #else
838 odm_allocate_memory(dm, (void **)&buf->octet, buf->buffer_size);
839
840 if (!buf->octet)
841 ret = false;
842 #endif
843
844 if (ret)
845 buf->length = buf->buffer_size;
846 }
847
848 return ret;
849 }
850
phydm_la_access_tx_pkt_buf(void * dm_void,u32 addr,u32 buff_idx)851 void phydm_la_access_tx_pkt_buf(void *dm_void, u32 addr, u32 buff_idx)
852 {
853 struct dm_struct *dm = (struct dm_struct *)dm_void;
854 struct rt_adcsmp *smp = &dm->adcsmp;
855 struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
856 u32 page;
857 u32 data_l = 0, data_h = 0;
858
859 #if (RTL8192F_SUPPORT)
860 if (dm->support_ic_type & ODM_RTL8192F) {
861 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
862 indirect_access_sdram_8192f(dm->adapter, TX_PACKET_BUFFER,
863 TRUE, (u16)addr >> 3, 0,
864 &data_h, &data_l);
865 #else
866 odm_write_1byte(dm, R_0x0106, 0x69);
867 odm_set_mac_reg(dm, R_0x0140, MASKDWORD, addr >> 3);
868 data_l = odm_get_mac_reg(dm, R_0x0144, MASKDWORD);
869 data_h = odm_get_mac_reg(dm, R_0x0148, MASKDWORD);
870 odm_write_1byte(dm, R_0x0106, 0x0);
871 #endif
872 } else
873 #endif
874 {
875 /* Reg140=0x780+(addr>>12),
876 * addr=0x30~0x3F, total 16 pages
877 */
878 page = addr >> 12;
879
880 if (page != smp->txff_page) {
881 smp->txff_page = page;
882 odm_set_mac_reg(dm, R_0x0140, MASKLWORD, 0x780 + page);
883 }
884 data_l = odm_read_4byte(dm, R_0x8000 + (addr & 0xfff));
885 data_h = odm_read_4byte(dm, R_0x8000 + (addr & 0xfff) + 4);
886 }
887
888 buf->octet[buff_idx] = data_h;
889 buf->octet[buff_idx + 1] = data_l;
890
891 /*@==== [Print LA Patterns] ==========================================*/
892 if (smp->is_la_print)
893 pr_debug("%08x%08x\n", data_h, data_l);
894 }
895
phydm_la_get_tx_pkt_buf(void * dm_void)896 void phydm_la_get_tx_pkt_buf(void *dm_void)
897 {
898 struct dm_struct *dm = (struct dm_struct *)dm_void;
899 struct rt_adcsmp *smp = &dm->adcsmp;
900 struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
901 u32 i = 0, value32 = 0;
902 u32 addr = 0, finish_addr = 0; /* @(unit: 8Byte)*/
903 boolean is_round_up = false;
904 u32 addr_8byte = 0;
905 u32 round_up_point = 0;
906 u32 index = 0;
907 u32 imem_base;
908 u32 txbuf_base;
909 u32 dma_len;
910 u32 imem_start_addr;
911 u32 imem_start_addr_offset;
912 u32 txbuff_start_addr;
913 u32 tx_buff_addr;
914
915 #if (RTL8814B_SUPPORT)
916 boolean recover_success = true;
917 #endif
918
919 odm_memory_set(dm, buf->octet, 0, buf->length);
920 pr_debug("GetTxPktBuf\n");
921
922 /*@==== [Get LA Report] ==============================================*/
923 if (dm->support_ic_type & ODM_RTL8192F) {
924 value32 = odm_read_4byte(dm, R_0x7f0);
925 is_round_up = (boolean)((value32 & BIT(31)) >> 31);
926 finish_addr = (value32 & 0x7FFF8000) >> 15; /*@16 bit (unit: 8Byte)*/
927 } else {
928 odm_write_1byte(dm, R_0x0106, 0x69);
929 value32 = odm_read_4byte(dm, R_0x7c0);
930 is_round_up = (boolean)((value32 & BIT(31)) >> 31);
931
932 if (dm->support_ic_type & PHYDM_LA_STORE_IN_IMEM_IC)
933 finish_addr = (value32 & 0x7FFF8000) >> 15; /*@16 bit (unit: 8Byte)*/
934 else
935 finish_addr = (value32 & 0x7FFF0000) >> 16; /*@15bit (unit: 8Byte)*/
936 }
937
938 #if (RTL8814B_SUPPORT)
939 recover_success = phydm_la_finish_addr_recover_8814B(dm, &finish_addr);
940 #endif
941
942 pr_debug("start_addr = ((0x%x)), end_addr = ((0x%x)), buffer_size = ((0x%x))\n",
943 buf->start_pos, buf->end_pos, buf->buffer_size);
944 if (is_round_up) {
945 pr_debug("buf_start(0x%x)|----2---->|finish_addr(0x%x)|----1---->|buf_end(0x%x)\n",
946 buf->start_pos, finish_addr << 3, buf->end_pos);
947 addr = (finish_addr + 2) << 3; /*+1 or +2 ??*/
948 round_up_point = (buf->end_pos - addr) >> 3; /*@Byte to 8Byte*/
949 smp->smp_number = smp->smp_number_max;
950 pr_debug("is_round_up=(%d), round_up_point=(%d), 0x7c0/0x7F0=(0x%x), smp_number=(%d)\n",
951 is_round_up, round_up_point, value32, smp->smp_number);
952 } else {
953 pr_debug("buf_start(0x%x)|------->|finish_addr(0x%x) |buf_end(0x%x)\n",
954 buf->start_pos, finish_addr << 3, buf->end_pos);
955 addr = buf->start_pos;
956 addr_8byte = addr >> 3;
957 smp->smp_number = DIFF_2(addr_8byte, finish_addr);
958
959 pr_debug("is_round_up=(%d), smp_number=(%d)\n",
960 is_round_up, smp->smp_number);
961 }
962
963 /*@==== [Get LA Patterns in TXFF] ====================================*/
964 pr_debug("Dump_Start\n");
965 #if(RTL8723F_SUPPORT)
966 imem_base = 0x14040000;
967 txbuf_base = 0x18780000;
968 dma_len = 0x8000;
969 txbuff_start_addr = txbuf_base;
970 imem_start_addr_offset = addr;
971 if (is_round_up) {
972 for(index = 0;index < 4;index++) {
973 dma_len = 0x8000;
974 imem_start_addr= imem_base + (imem_start_addr_offset&0x1FFFF);
975
976 if((imem_start_addr_offset + 0x8000) >= buf->end_pos) {
977 dma_len = buf->end_pos-imem_start_addr_offset;
978
979 phydm_la_mv_data_2_tx_buffer_rtl8723f(dm, imem_start_addr, txbuff_start_addr, dma_len);
980
981 tx_buff_addr = 0;
982 for (i = 0; i < (dma_len >> 3); i++) {
983 phydm_la_access_tx_pkt_buf(dm, tx_buff_addr, i << 1);
984 tx_buff_addr += 8;
985 }
986 imem_start_addr = imem_base;
987 dma_len = 0x8000-dma_len;
988 phydm_la_mv_data_2_tx_buffer_rtl8723f(dm, imem_start_addr, txbuff_start_addr, dma_len);
989
990 tx_buff_addr = 0;
991 for (i = 0; i < (dma_len >> 3); i++) {
992 phydm_la_access_tx_pkt_buf(dm, tx_buff_addr, i << 1);
993 tx_buff_addr += 8;
994 }
995 imem_start_addr_offset = dma_len;
996 }
997 else {
998 dma_len = 0x8000;
999 phydm_la_mv_data_2_tx_buffer_rtl8723f(dm, imem_start_addr, txbuff_start_addr, dma_len);
1000
1001 tx_buff_addr = 0;
1002 for (i = 0; i <4096; i++) {
1003 phydm_la_access_tx_pkt_buf(dm, tx_buff_addr, i << 1);
1004 tx_buff_addr += 8;
1005 }
1006 imem_start_addr_offset += 0x8000;
1007 }
1008 }
1009 } else {
1010 for(index = 0; index < 4;index++) {
1011 imem_start_addr = imem_base + (imem_start_addr_offset & 0x1FFFF);
1012 if ((imem_start_addr_offset + 0x8000) > (finish_addr << 3))
1013 dma_len = (finish_addr << 3) - imem_start_addr_offset; /*0x1208[17:0]:DMA Length*/
1014 phydm_la_mv_data_2_tx_buffer_rtl8723f(dm,imem_start_addr, txbuff_start_addr, dma_len);
1015 tx_buff_addr = 0;
1016 for (i = 0; i < (dma_len >> 3); i++) {
1017 phydm_la_access_tx_pkt_buf(dm, tx_buff_addr, i << 1);
1018 tx_buff_addr += 8;
1019 }
1020 dma_len = 0x8000;
1021 imem_start_addr_offset += 0x8000;
1022 if (imem_start_addr_offset > (finish_addr << 3))
1023 break;
1024 }
1025 }
1026 #else
1027
1028 #ifdef PHYDM_COMPILE_LA_STORE_IN_IMEM
1029 phydm_la_mv_data_2_tx_buffer(dm);
1030 #endif
1031
1032 #if (RTL8814B_SUPPORT)
1033 if ((dm->support_ic_type & ODM_RTL8814B) && !recover_success) {
1034 addr = buf->start_pos;
1035 smp->smp_number = smp->smp_number_max;
1036 }
1037 #endif
1038
1039 for (i = 0; i < smp->smp_number; i++) {
1040 phydm_la_access_tx_pkt_buf(dm, addr, i << 1);
1041 addr += 8;
1042
1043 if (addr >= buf->end_pos)
1044 addr = buf->start_pos; /*Ring buffer*/
1045 }
1046
1047 #if (RTL8197F_SUPPORT)
1048 phydm_la_stop_dma_8197f(dm, PHYDM_RESTORE);
1049 #endif
1050 #endif
1051 pr_debug("Dump_End\n");
1052 }
1053
phydm_la_set_trig_src(void * dm_void,u8 la_trig_mode)1054 void phydm_la_set_trig_src(void *dm_void, u8 la_trig_mode)
1055 {
1056 struct dm_struct *dm = (struct dm_struct *)dm_void;
1057 u32 reg = (dm->support_ic_type == ODM_RTL8192F) ? R_0x7f0 : R_0x7c0;
1058
1059 if (la_trig_mode == PHYDM_ADC_MAC_TRIG)
1060 odm_set_mac_reg(dm, reg, BIT(3), 1);
1061 else
1062 odm_set_mac_reg(dm, reg, BIT(3), 0);
1063 }
1064
phydm_la_set_mac_iq_dump(void * dm_void,boolean impossible_trig_condi)1065 void phydm_la_set_mac_iq_dump(void *dm_void, boolean impossible_trig_condi)
1066 {
1067 struct dm_struct *dm = (struct dm_struct *)dm_void;
1068 struct rt_adcsmp *smp = &dm->adcsmp;
1069 u32 reg_value = 0;
1070 u32 reg1 = 0, reg2 = 0, reg3 = 0;
1071
1072 if (dm->support_ic_type & ODM_RTL8192F) {
1073 reg1 = R_0x7f0;
1074 reg2 = R_0x7f4;
1075 reg3 = R_0x7f8;
1076 } else {
1077 reg1 = R_0x7c0;
1078 reg2 = R_0x7c4;
1079 reg3 = R_0x7c8;
1080 }
1081
1082 odm_write_1byte(dm, reg1, 0); /*@clear all reg1*/
1083 /*@Enable LA mode HW block*/
1084 odm_set_mac_reg(dm, reg1, BIT(0), 1);
1085
1086 #if (RTL8723F_SUPPORT)
1087 if (dm->support_ic_type & ODM_RTL8723F)
1088 phydm_la_mac_clk_en(dm, true);
1089 #endif
1090
1091 if (smp->la_trig_mode == PHYDM_MAC_TRIG) {
1092 smp->la_dump_mode = LA_MAC_DBG_DUMP;
1093 /*polling bit for MAC mode*/
1094 odm_set_mac_reg(dm, reg1, BIT(2), 1);
1095 /*trigger mode for MAC*/
1096 odm_set_mac_reg(dm, reg1, 0x18, smp->la_trigger_edge);
1097 pr_debug("[MAC_trig] ref_mask=(0x%x), ref_value=(0x%x), dbg_port =(0x%x)\n",
1098 smp->la_mac_mask_or_hdr_sel, smp->la_trig_sig_sel,
1099 smp->la_dbg_port);
1100 /*@[Set MAC Debug Port]*/
1101 odm_set_mac_reg(dm, R_0xf4, BIT(16), 1);
1102 odm_set_mac_reg(dm, R_0x38, 0xff0000, smp->la_dbg_port);
1103 odm_set_mac_reg(dm, reg2, MASKDWORD,
1104 smp->la_mac_mask_or_hdr_sel);
1105 odm_set_mac_reg(dm, reg3, MASKDWORD, smp->la_trig_sig_sel);
1106 } else {
1107 smp->la_dump_mode = LA_BB_ADC_DUMP;
1108
1109 if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) {
1110 /*polling bit for MAC trigger event*/
1111 if (impossible_trig_condi)
1112 phydm_la_set_trig_src(dm, PHYDM_ADC_BB_TRIG);
1113 else
1114 phydm_la_set_trig_src(dm, PHYDM_ADC_MAC_TRIG);
1115
1116 odm_set_mac_reg(dm, reg1, 0xc0, smp->la_trig_sig_sel);
1117
1118 if (smp->la_trig_sig_sel == ADCSMP_TRIG_REG) {
1119 /* @manual trigger reg1[5] = 0->1*/
1120 odm_set_mac_reg(dm, reg1, BIT(5), 1);
1121 }
1122 }
1123 /*polling bit for BB ADC mode*/
1124 odm_set_mac_reg(dm, reg1, BIT(1), 1);
1125 }
1126
1127 reg_value = odm_get_mac_reg(dm, reg1, 0xff);
1128 pr_debug("4. [Set MAC IQ dump] 0x%x[7:0]=(0x%x)\n", reg1, reg_value);
1129
1130 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1131 RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
1132 ("4. [Set MAC IQ dump] 0x%x[7:0]=(0x%x)\n", reg1,
1133 reg_value));
1134 #endif
1135 }
1136
phydm_la_set_bb_dbg_port(void * dm_void,boolean impossible_trig_condi)1137 void phydm_la_set_bb_dbg_port(void *dm_void, boolean impossible_trig_condi)
1138 {
1139 struct dm_struct *dm = (struct dm_struct *)dm_void;
1140 struct rt_adcsmp *smp = &dm->adcsmp;
1141
1142 u8 trig_mode = smp->la_trig_mode;
1143 u32 trig_sel = smp->la_trig_sig_sel;
1144 u32 dbg_port = smp->la_dbg_port;
1145
1146 if (trig_mode == PHYDM_MAC_TRIG)
1147 trig_sel = 0; /*@ignore this setting*/
1148
1149 /*set BB debug port*/
1150 if (impossible_trig_condi) {
1151 dbg_port = 0xf;
1152 trig_sel = 0;
1153 pr_debug("[BB Setting] fake-trigger!\n");
1154 }
1155
1156 if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbg_port)) {
1157 pr_debug(" *Set dbg_port=(0x%x)\n", dbg_port);
1158 } else {
1159 dbg_port = phydm_get_bb_dbg_port_idx(dm);
1160 pr_debug("[Set dbg_port fail!] Curr-DbgPort=0x%x\n", dbg_port);
1161 }
1162
1163 /*@debug port bit*/
1164 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
1165 odm_set_bb_reg(dm, R_0x95c, 0x1f, trig_sel);
1166 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
1167 } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1168 odm_set_bb_reg(dm, R_0x1ce4, 0x3e000, trig_sel);
1169 #endif
1170 } else {
1171 odm_set_bb_reg(dm, R_0x9a0, 0x1f, trig_sel);
1172 }
1173
1174 if (smp->la_trig_mode == PHYDM_ADC_BB_TRIG) {
1175 pr_debug(" *Set dbg_port[BIT] = %d\n", trig_sel);
1176
1177 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1178 RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
1179 (" *Set dbg_port[BIT] = %d\n", trig_sel));
1180 #endif
1181 }
1182 }
1183
phydm_la_set_bb(void * dm_void)1184 void phydm_la_set_bb(void *dm_void)
1185 {
1186 struct dm_struct *dm = (struct dm_struct *)dm_void;
1187 struct rt_adcsmp *smp = &dm->adcsmp;
1188
1189 u8 trig_mode = smp->la_trig_mode;
1190 u8 edge = smp->la_trigger_edge;
1191 u8 smp_rate = smp->la_smp_rate;
1192 u8 dma_type = smp->la_dma_type;
1193 u32 dbg_port_hdr_sel = 0;
1194 char *trig_mode_word = NULL;
1195
1196 pr_debug("3. [BB Setting] mode=(%d), Edge=(%s), smp_rate=(%dM), Dma_type=(%d)\n",
1197 trig_mode,
1198 (edge == 0) ? "P" : "N", 80 >> smp_rate, dma_type);
1199
1200 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
1201 if (trig_mode == PHYDM_ADC_RF0_TRIG)
1202 dbg_port_hdr_sel = 9; /*@DBGOUT_RFC_a[31:0]*/
1203 else if (trig_mode == PHYDM_ADC_RF1_TRIG)
1204 dbg_port_hdr_sel = 8; /*@DBGOUT_RFC_b[31:0]*/
1205 else if ((trig_mode == PHYDM_ADC_BB_TRIG) ||
1206 (trig_mode == PHYDM_ADC_MAC_TRIG)) {
1207 if (smp->la_mac_mask_or_hdr_sel <= 0xf)
1208 dbg_port_hdr_sel = smp->la_mac_mask_or_hdr_sel;
1209 else
1210 dbg_port_hdr_sel = 0;
1211 }
1212
1213 phydm_bb_dbg_port_header_sel(dm, dbg_port_hdr_sel);
1214
1215 odm_set_bb_reg(dm, R_0x8b4, BIT(7), 1);/*@update rpt every pkt*/
1216 odm_set_bb_reg(dm, R_0x95c, 0xf00, dma_type);
1217 /*@0: posedge, 1: negedge*/
1218 odm_set_bb_reg(dm, R_0x95c, BIT(31), edge);
1219 odm_set_bb_reg(dm, R_0x95c, 0xe0, smp_rate);
1220 /* @(0:) '80MHz'
1221 * (1:) '40MHz'
1222 * (2:) '20MHz'
1223 * (3:) '10MHz'
1224 * (4:) '5MHz'
1225 * (5:) '2.5MHz'
1226 * (6:) '1.25MHz'
1227 * (7:) '160MHz (for BW160 ic)'
1228 */
1229 #if (RTL8821C_SUPPORT || RTL8195B_SUPPORT)
1230 phydm_la_clk_en(dm, true);
1231 #endif
1232
1233 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
1234 } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1235 odm_set_bb_reg(dm, R_0x1eb4, BIT(23), 0x1);/*@update rpt every pkt*/
1236 /*@MAC-PHY timing*/
1237 odm_set_bb_reg(dm, R_0x1ce4, BIT(7) | BIT(6), 0);
1238 odm_set_bb_reg(dm, R_0x1cf4, BIT(23), 1); /*@LA mode on*/
1239 odm_set_bb_reg(dm, R_0x1ce4, 0x3f, dma_type);
1240 /*@0: posedge, 1: negedge ??*/
1241 odm_set_bb_reg(dm, R_0x1ce4, BIT(26), edge);
1242 odm_set_bb_reg(dm, R_0x1ce4, 0x700, smp_rate);
1243
1244 phydm_la_bb_adv_trig_setting_jgr3(dm);
1245 #endif
1246 } else {
1247 if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
1248 odm_set_bb_reg(dm, R_0xd00, BIT(26), 0x1); /*@update rpt every pkt*/
1249
1250 #if (RTL8192F_SUPPORT)
1251 if ((dm->support_ic_type & ODM_RTL8192F))
1252 /*@LA reset HW block enable for true-mac asic*/
1253 odm_set_bb_reg(dm, R_0x9a0, BIT(15), 1);
1254 #endif
1255
1256 odm_set_bb_reg(dm, R_0x9a0, 0xf00, dma_type);
1257 /*@0: posedge, 1: negedge*/
1258 odm_set_bb_reg(dm, R_0x9a0, BIT(31), edge);
1259 odm_set_bb_reg(dm, R_0x9a0, 0xe0, smp_rate);
1260 /* @(0:) '80MHz'
1261 * (1:) '40MHz'
1262 * (2:) '20MHz'
1263 * (3:) '10MHz'
1264 * (4:) '5MHz'
1265 * (5:) '2.5MHz'
1266 * (6:) '1.25MHz'
1267 * (7:) '160MHz (for BW160 ic)'
1268 */
1269 }
1270 }
1271
phydm_la_set_mac_trigger_time(void * dm_void,u32 trigger_time_mu_sec)1272 void phydm_la_set_mac_trigger_time(void *dm_void, u32 trigger_time_mu_sec)
1273 {
1274 struct dm_struct *dm = (struct dm_struct *)dm_void;
1275 u8 time_unit_num = 0;
1276 u32 unit = 0;
1277
1278 if (trigger_time_mu_sec < 128)
1279 unit = 0; /*unit: 1mu sec*/
1280 else if (trigger_time_mu_sec < 256)
1281 unit = 1; /*unit: 2mu sec*/
1282 else if (trigger_time_mu_sec < 512)
1283 unit = 2; /*unit: 4mu sec*/
1284 else if (trigger_time_mu_sec < 1024)
1285 unit = 3; /*unit: 8mu sec*/
1286 else if (trigger_time_mu_sec < 2048)
1287 unit = 4; /*unit: 16mu sec*/
1288 else if (trigger_time_mu_sec < 4096)
1289 unit = 5; /*unit: 32mu sec*/
1290 else if (trigger_time_mu_sec < 8192)
1291 unit = 6; /*unit: 64mu sec*/
1292 else if (trigger_time_mu_sec < 16384)
1293 if (dm->support_ic_type & ODM_RTL8723F)
1294 unit = 7; /*unit: 128mu sec*/
1295
1296 time_unit_num = (u8)(trigger_time_mu_sec >> unit);
1297
1298 pr_debug("2. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n",
1299 time_unit_num, unit);
1300 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1301 RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, (
1302 "3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n",
1303 time_unit_num, unit));
1304 #endif
1305
1306 if (dm->support_ic_type & ODM_RTL8192F) {
1307 odm_set_mac_reg(dm, R_0x7fc, BIT(2) | BIT(1) | BIT(0), unit);
1308 odm_set_mac_reg(dm, R_0x7f0, 0x7f00, (time_unit_num & 0x7f));
1309 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
1310 } else if (dm->support_ic_type & ODM_RTL8814B) {
1311 odm_set_mac_reg(dm, R_0x7cc, BIT(20) | BIT(19) | BIT(18), unit);
1312 odm_set_mac_reg(dm, R_0x7c0, 0x7f00, (time_unit_num & 0x7f));
1313 } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1314 odm_set_mac_reg(dm, R_0x7cc, BIT(18) | BIT(17) | BIT(16), unit);
1315 odm_set_mac_reg(dm, R_0x7c0, 0x7f00, (time_unit_num & 0x7f));
1316 #endif
1317 } else {
1318 odm_set_mac_reg(dm, R_0x7cc, BIT(20) | BIT(19) | BIT(18), unit);
1319 odm_set_mac_reg(dm, R_0x7c0, 0x7f00, (time_unit_num & 0x7f));
1320 }
1321 }
1322
phydm_la_set_buff_mode(void * dm_void,enum la_buff_mode mode)1323 void phydm_la_set_buff_mode(void *dm_void, enum la_buff_mode mode)
1324 {
1325 struct dm_struct *dm = (struct dm_struct *)dm_void;
1326 struct rt_adcsmp *smp = &dm->adcsmp;
1327 struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
1328 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
1329 struct rtl8192cd_priv *priv = dm->priv;
1330 u8 normal_LA_on = priv->pmib->miscEntry.normal_LA_on;
1331 #endif
1332 u32 buff_size_base = 0;
1333 u32 end_pos_tmp = 0;
1334
1335 smp->la_buff_mode = mode;
1336 switch (dm->support_ic_type) {
1337 case ODM_RTL8814A:
1338 buff_size_base = 0x10000;
1339 end_pos_tmp = 0x40000;
1340 break;
1341 case ODM_RTL8822B:
1342 case ODM_RTL8822C:
1343 case ODM_RTL8812F:
1344 buff_size_base = 0x20000; /*@WIN: TX_FIFO_SIZE_LA_8822C*/
1345 end_pos_tmp = 0x40000;
1346 break;
1347 case ODM_RTL8814B:
1348 buff_size_base = 0x30000;
1349 end_pos_tmp = 0x60000;
1350 break;
1351 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
1352 case ODM_RTL8197F:
1353 case ODM_RTL8198F:
1354 case ODM_RTL8197G:
1355 buff_size_base = 0x10000;
1356 end_pos_tmp = (normal_LA_on == 1) ? 0x20000 : 0x10000;
1357 break;
1358 #endif
1359 case ODM_RTL8192F:
1360 buff_size_base = 0xE000;
1361 end_pos_tmp = 0x10000;
1362 break;
1363 case ODM_RTL8821C:
1364 buff_size_base = 0x8000;
1365 end_pos_tmp = 0x10000;
1366 break;
1367 case ODM_RTL8195B:
1368 buff_size_base = 0x4000;
1369 end_pos_tmp = 0x8000;
1370 break;
1371 case ODM_RTL8723F:
1372 buff_size_base = 0x20000;
1373 end_pos_tmp = 0x20000;
1374 break;
1375 default:
1376 pr_debug("[%s] Warning!", __func__);
1377 break;
1378 }
1379
1380 buf->buffer_size = buff_size_base;
1381
1382 if (dm->support_ic_type & ODM_RTL8814B) {
1383 if (mode == ADCSMP_BUFF_HALF) {
1384 odm_set_mac_reg(dm, R_0x7cc, BIT(21), 0);
1385 } else {
1386 buf->buffer_size = buf->buffer_size << 1;
1387 odm_set_mac_reg(dm, R_0x7cc, BIT(21), 1);
1388 }
1389 } else if (dm->support_ic_type & FULL_BUFF_MODE_SUPPORT) {
1390 if (mode == ADCSMP_BUFF_HALF) {
1391 odm_set_mac_reg(dm, R_0x7cc, BIT(30), 0);
1392 } else {
1393 buf->buffer_size = buf->buffer_size << 1;
1394 odm_set_mac_reg(dm, R_0x7cc, BIT(30), 1);
1395 }
1396 }
1397
1398 buf->end_pos = end_pos_tmp;
1399 buf->start_pos = end_pos_tmp - buf->buffer_size;
1400 smp->smp_number_max = buf->buffer_size >> 3;
1401
1402 pr_debug("start_addr=(0x%x), end_addr=(0x%x), buffer_size=(0x%x), smp_number_max=(%d)\n",
1403 buf->start_pos, buf->end_pos, buf->buffer_size,
1404 smp->smp_number_max);
1405 }
1406
phydm_la_adc_smp_start(void * dm_void)1407 void phydm_la_adc_smp_start(void *dm_void)
1408 {
1409 struct dm_struct *dm = (struct dm_struct *)dm_void;
1410 struct rt_adcsmp *smp = &dm->adcsmp;
1411 u8 tmp_u1b = 0;
1412 u8 i = 0;
1413 u8 polling_bit = 0;
1414 u8 bkp_val = 0;
1415 boolean polling_ok = false;
1416 boolean impossible_trig_condi = (smp->en_fake_trig) ? true : false;
1417
1418 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1419 RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
1420 ("1. [BB Setting] Mode=(%d), DbgPort=(0x%x), Edge=(%d), SmpRate=(%d), Trig_Sel=(0x%x), Dma_type=(%d)\n",
1421 smp->la_trig_mode, smp->la_dbg_port, smp->la_trigger_edge,
1422 smp->la_smp_rate, smp->la_trig_sig_sel, smp->la_dma_type));
1423 #endif
1424 pr_debug("1. [BB Setting] trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x)), Dma_type = ((%d))\n",
1425 smp->la_trig_mode, smp->la_dbg_port, smp->la_trigger_edge,
1426 smp->la_smp_rate, smp->la_trig_sig_sel, smp->la_dma_type);
1427
1428 if(dm->support_ic_type & ODM_RTL8723F)
1429 bkp_val = (u8)odm_get_mac_reg(dm, R_0x1008, BIT(1));
1430
1431 phydm_la_set_mac_trigger_time(dm, smp->la_trigger_time);
1432 phydm_la_set_bb(dm);
1433 phydm_la_set_bb_dbg_port(dm, impossible_trig_condi);
1434 phydm_la_set_mac_iq_dump(dm, impossible_trig_condi);
1435
1436 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1437 watchdog_stop(dm->priv);
1438 #endif
1439
1440 if (impossible_trig_condi) {
1441 ODM_delay_ms(100);
1442 phydm_la_set_bb_dbg_port(dm, false);
1443
1444 if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) {
1445 phydm_la_set_trig_src(dm, PHYDM_ADC_MAC_TRIG);
1446 }
1447 }
1448 #if RTL8198F_SUPPORT
1449 phydm_la_pre_run(dm);
1450 #endif
1451 polling_bit = (smp->la_dump_mode == LA_BB_ADC_DUMP) ? BIT(1) : BIT(2);
1452 do { /*Polling time always use 100ms, when it exceed 2s, break loop*/
1453 if (dm->support_ic_type & ODM_RTL8192F)
1454 tmp_u1b = odm_read_1byte(dm, R_0x7f0);
1455 else
1456 tmp_u1b = odm_read_1byte(dm, R_0x7c0);
1457
1458 pr_debug("[%d] polling rpt=((0x%x))\n", i, tmp_u1b);
1459
1460 if (smp->adc_smp_state != ADCSMP_STATE_SET) {
1461 pr_debug("[state Error] state != ADCSMP_STATE_SET\n");
1462 break;
1463
1464 } else if (tmp_u1b & polling_bit) {
1465 ODM_delay_ms(100);
1466 i++;
1467 continue;
1468 } else {
1469 pr_debug("[LA Query OK] polling_bit=%d\n", polling_bit);
1470 polling_ok = true;
1471 break;
1472 }
1473 } while (i < 20);
1474
1475 if (smp->adc_smp_state == ADCSMP_STATE_SET) {
1476 if (polling_ok)
1477 phydm_la_get_tx_pkt_buf(dm);
1478 else
1479 pr_debug("[Polling timeout]\n");
1480 }
1481
1482 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1483 watchdog_resume(dm->priv);
1484 #endif
1485
1486 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1487 if (smp->adc_smp_state == ADCSMP_STATE_SET)
1488 smp->adc_smp_state = ADCSMP_STATE_QUERY;
1489 #endif
1490
1491 pr_debug("[LA mode] la_count = ((%d))\n", smp->la_count);
1492 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1493 RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
1494 ("[LA mode] la_count = ((%d))\n", smp->la_count));
1495 #endif
1496
1497 phydm_la_stop(dm);
1498
1499 if (smp->la_count == 0) {
1500 pr_debug("LA Dump finished ---------->\n\n\n");
1501 phydm_release_bb_dbg_port(dm);
1502
1503 #if (RTL8821C_SUPPORT || RTL8195B_SUPPORT)
1504 phydm_la_clk_en(dm, false);
1505 #endif
1506 #if (RTL8723F_SUPPORT)
1507 if(dm->support_ic_type & ODM_RTL8723F)
1508 phydm_la_mac_clk_en(dm, (bkp_val == 1) ? true : false);
1509 #endif
1510 } else {
1511 smp->la_count--;
1512 pr_debug("LA Dump more ---------->\n\n\n");
1513 phydm_la_set(dm);
1514 }
1515 }
1516
phydm_la_set(void * dm_void)1517 void phydm_la_set(void *dm_void)
1518 {
1519 struct dm_struct *dm = (struct dm_struct *)dm_void;
1520 boolean is_set_success = true;
1521 struct rt_adcsmp *smp = &dm->adcsmp;
1522
1523 if (smp->adc_smp_state != ADCSMP_STATE_IDLE)
1524 is_set_success = false;
1525 else if (smp->adc_smp_buf.length == 0)
1526 is_set_success = phydm_la_buffer_allocate(dm);
1527
1528 if (!is_set_success) {
1529 pr_debug("[LA Set Fail] LA_State=(%d)\n", smp->adc_smp_state);
1530 return;
1531 }
1532
1533 smp->adc_smp_state = ADCSMP_STATE_SET;
1534
1535 pr_debug("[LA Set Success] LA_State=(%d)\n", smp->adc_smp_state);
1536
1537 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1538
1539 pr_debug("ADCSmp_work_item_index=(%d)\n", smp->la_work_item_index);
1540
1541 if (smp->la_work_item_index != 0) {
1542 odm_schedule_work_item(&smp->adc_smp_work_item_1);
1543 smp->la_work_item_index = 0;
1544 } else {
1545 odm_schedule_work_item(&smp->adc_smp_work_item);
1546 smp->la_work_item_index = 1;
1547 }
1548 #else
1549 phydm_la_adc_smp_start(dm);
1550 #endif
1551 }
1552
phydm_la_cmd(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)1553 void phydm_la_cmd(void *dm_void, char input[][16], u32 *_used, char *output,
1554 u32 *_out_len)
1555 {
1556 struct dm_struct *dm = (struct dm_struct *)dm_void;
1557 struct rt_adcsmp *smp = &dm->adcsmp;
1558 char help[] = "-h";
1559 u32 var1[10] = {0};
1560 u32 used = *_used;
1561 u32 out_len = *_out_len;
1562
1563 if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE))
1564 return;
1565
1566 #ifdef PHYDM_COMPILE_LA_STORE_IN_IMEM
1567 if (dm->support_ic_type & PHYDM_LA_STORE_IN_IMEM_IC) {
1568 if (dm->is_download_fw)
1569 return;
1570 }
1571 #if RTL8198F_SUPPORT
1572 if (dm->support_ic_type & ODM_RTL8198F) {
1573 if (!*dm->mp_mode && !dm->priv->pmib->miscEntry.normal_LA_on) {
1574 pr_debug("plz re-set normal_LA_on = 1 & DnUp.\n");
1575 return;
1576 }
1577 }
1578 #endif
1579 #endif
1580
1581 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
1582
1583 /*@dbg_print("echo cmd input_num = %d\n", input_num);*/
1584
1585 if ((strcmp(input[1], help) == 0)) {
1586 PDM_SNPF(out_len, used, output + used, out_len - used,
1587 "=====[LA Mode Help] =============================\n");
1588 /*Trigger*/
1589 PDM_SNPF(out_len, used, output + used, out_len - used,
1590 "BB_trig: 1 0 {DbgPort Bit} {DMA#} {TrigTime} {DbgPort_head(Jgr2)}\n\t{DbgPort} {Edge: 0(P),1(N)} {f_smp:80 >> N} {Capture num}\n\n");
1591 PDM_SNPF(out_len, used, output + used, out_len - used,
1592 "MAC_trig: 1 1 {0-ok/1-fail/2-cca} {DMA#} {TrigTime} {DbgPort_head(Jgr2)}\n\t{DbgPort} {N/A} {f_smp:80 >> N} {Cpture num}\n\n");
1593 PDM_SNPF(out_len, used, output + used, out_len - used,
1594 "All: {En} {0:ADC_BB_trig,1:ADC MAC_trig,2:RF0,3:RF1,4:MAC}\n\t{BB:dbg_port[bit],BB_MAC:0-ok/1-fail/2-cca,MAC:ref} {DMA#} {TrigTime}\n\t{DbgPort_head/ref_mask} {dbg_port} {0:P_Edge, 1:N_Edge} {SpRate:0-80M,1-40M,2-20M} {Capture num}\n\n");
1595 /*Adv-Trig*/
1596 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
1597 PDM_SNPF(out_len, used, output + used, out_len - used,
1598 "adv show\n");
1599 PDM_SNPF(out_len, used, output + used, out_len - used,
1600 "adv {adv_trig_en} {0:And[0]_disable} {en}\n");
1601 PDM_SNPF(out_len, used, output + used, out_len - used,
1602 "adv {adv_trig_en} {1~3: And[3:0]} {Sel} {Val} {Inv}\n");
1603 PDM_SNPF(out_len, used, output + used, out_len - used,
1604 "adv {adv_trig_en} {4: And[4]} {BitMask} {BitVal} {Inv}\n\n");
1605 #endif
1606 /*Setting*/
1607 PDM_SNPF(out_len, used, output + used, out_len - used,
1608 "set {1:tx_buff_size} {0: half, 1:full}\n");
1609 PDM_SNPF(out_len, used, output + used, out_len - used,
1610 "set {2:Fake Trigger} {en}\n");
1611 PDM_SNPF(out_len, used, output + used, out_len - used,
1612 "set {3:Auto Print} {en}\n\n");
1613 /*Print*/
1614 PDM_SNPF(out_len, used, output + used, out_len - used,
1615 "print {0: all(Hex)}\n");
1616 PDM_SNPF(out_len, used, output + used, out_len - used,
1617 "print {1: partial} {0:hex 1:dec 2: s-dec} {bit_L} {bit_H}\n\n");
1618
1619 /*Fast Trigger*/
1620 PDM_SNPF(out_len, used, output + used, out_len - used,
1621 "fast {0: CCA trig & AGC Dbg Port}\n");
1622 PDM_SNPF(out_len, used, output + used, out_len - used,
1623 "fast {1: CCA trig & EVM Dbg Port}\n");
1624 PDM_SNPF(out_len, used, output + used, out_len - used,
1625 "fast {2: CCA trig & SNR Dbg Port}\n");
1626 PDM_SNPF(out_len, used, output + used, out_len - used,
1627 "fast {3: CCA trig & CFO Dbg Port}\n");
1628 PDM_SNPF(out_len, used, output + used, out_len - used,
1629 "fast {4: CCA trig & ADC output Dbg Port}\n");
1630 PDM_SNPF(out_len, used, output + used, out_len - used,
1631 "fast {10: EVM>=-X dB, 11: EVM<=-X dB} {X=2/4/8/16/32/64} {0:Lgcy, 1:HT}\n");
1632 PDM_SNPF(out_len, used, output + used, out_len - used,
1633 "fast {12: EVM=-X dB} {X} {0:Lgcy, 1:HT}\n");
1634 PDM_SNPF(out_len, used, output + used, out_len - used,
1635 "fast {20: RX-rate-idx=X} {X}\n");
1636
1637 PDM_SNPF(out_len, used, output + used, out_len - used,
1638 "=================================================\n");
1639 } else if ((strcmp(input[1], "print") == 0)) {
1640 phydm_la_buffer_print(dm, input, &used, output, &out_len);
1641 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
1642 } else if ((strcmp(input[1], "fast") == 0)) {
1643 phydm_la_cmd_fast_jgr3(dm, input, &used, output, &out_len);
1644
1645 } else if ((strcmp(input[1], "adv") == 0)) {
1646 phydm_la_bb_adv_cmd_jgr3(dm, input, &used, output, &out_len);
1647 #endif
1648 } else if ((strcmp(input[1], "set") == 0)) {
1649 PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
1650
1651 if (var1[1] == 1) {
1652 PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
1653 phydm_la_set_buff_mode(dm, (enum la_buff_mode)var1[2]);
1654 PDM_SNPF(out_len, used, output + used, out_len - used,
1655 "Buff_mode=(%d/2)\n", smp->la_buff_mode + 1);
1656 } else if (var1[1] == 2) {
1657 PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
1658 smp->en_fake_trig = (boolean)var1[2];
1659
1660 PDM_SNPF(out_len, used, output + used, out_len - used,
1661 "en_fake_trig=(%d)\n", smp->en_fake_trig);
1662 } else if (var1[1] == 3) {
1663 PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
1664 smp->is_la_print = (boolean)var1[2];
1665 PDM_SNPF(out_len, used, output + used, out_len - used,
1666 "Auto print=(%d)\n", smp->is_la_print);
1667 }
1668 } else if (var1[0] == 1) {
1669 PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
1670
1671 smp->la_trig_mode = (u8)var1[1];
1672
1673 if (smp->la_trig_mode == PHYDM_MAC_TRIG)
1674 PHYDM_SSCANF(input[3], DCMD_HEX, &var1[2]);
1675 else
1676 PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
1677 smp->la_trig_sig_sel = var1[2];
1678
1679 PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);
1680 PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var1[4]);
1681 PHYDM_SSCANF(input[6], DCMD_HEX, &var1[5]);
1682 PHYDM_SSCANF(input[7], DCMD_HEX, &var1[6]);
1683 PHYDM_SSCANF(input[8], DCMD_DECIMAL, &var1[7]);
1684 PHYDM_SSCANF(input[9], DCMD_DECIMAL, &var1[8]);
1685 PHYDM_SSCANF(input[10], DCMD_DECIMAL, &var1[9]);
1686
1687 smp->la_dma_type = (u8)var1[3];
1688 smp->la_trigger_time = var1[4]; /*unit: us*/
1689 smp->la_mac_mask_or_hdr_sel = var1[5];
1690 smp->la_dbg_port = var1[6];
1691 smp->la_trigger_edge = (u8)var1[7];
1692 smp->la_smp_rate = (u8)(var1[8] & 0x7);
1693 smp->la_count = var1[9];
1694
1695 pr_debug("echo lamode %d %d %d %d %d %d %x %d %d %d\n",
1696 var1[0], var1[1], var1[2], var1[3], var1[4],
1697 var1[5], var1[6], var1[7], var1[8], var1[9]);
1698 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1699 RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
1700 ("echo lamode %d %d %d %d %d %d %x %d %d %d\n",
1701 var1[0], var1[1], var1[2], var1[3],
1702 var1[4], var1[5], var1[6], var1[7],
1703 var1[8], var1[9]));
1704 #endif
1705
1706 PDM_SNPF(out_len, used, output + used, out_len - used,
1707 "a.En= ((1)), b.mode = ((%d)), c.Trig_Sel = ((0x%x)), d.Dma_type = ((%d))\n",
1708 smp->la_trig_mode, smp->la_trig_sig_sel,
1709 smp->la_dma_type);
1710 PDM_SNPF(out_len, used, output + used, out_len - used,
1711 "e.Trig_Time = ((%dus)), f.Dbg_head/mac_ref_mask = ((0x%x)), g.dbg_port = ((0x%x))\n",
1712 smp->la_trigger_time,
1713 smp->la_mac_mask_or_hdr_sel, smp->la_dbg_port);
1714 PDM_SNPF(out_len, used, output + used, out_len - used,
1715 "h.Trig_edge = ((%d)), i.smp rate = ((%d MHz)), j.Cap_num = ((%d))\n",
1716 smp->la_trigger_edge, (80 >> smp->la_smp_rate),
1717 smp->la_count);
1718
1719 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
1720 PDM_SNPF(out_len, used, output + used, out_len - used,
1721 "k.en_new_bbtrigger = ((%d))\n",
1722 smp->adv_trig_table.la_adv_bbtrigger_en);
1723 #endif
1724
1725 phydm_la_set(dm);
1726 } else {
1727 phydm_la_stop(dm);
1728 PDM_SNPF(out_len, used, output + used, out_len - used,
1729 "Disable LA mode\n");
1730 }
1731
1732 *_used = used;
1733 *_out_len = out_len;
1734 }
1735
phydm_la_stop(void * dm_void)1736 void phydm_la_stop(void *dm_void)
1737 {
1738 struct dm_struct *dm = (struct dm_struct *)dm_void;
1739 struct rt_adcsmp *smp = &dm->adcsmp;
1740
1741 smp->adc_smp_state = ADCSMP_STATE_IDLE;
1742 }
1743
phydm_la_init(void * dm_void)1744 void phydm_la_init(void *dm_void)
1745 {
1746 struct dm_struct *dm = (struct dm_struct *)dm_void;
1747 struct rt_adcsmp *smp = &dm->adcsmp;
1748 struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
1749
1750 if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE))
1751 return;
1752
1753 smp->adc_smp_state = ADCSMP_STATE_IDLE;
1754 smp->is_la_print = true;
1755 smp->en_fake_trig = false;
1756 smp->txff_page = 0xffffffff;
1757 phydm_la_set_buff_mode(dm, ADCSMP_BUFF_HALF);
1758
1759 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
1760 phydm_la_bb_adv_reset_jgr3(dm);
1761 #endif
1762 }
1763
adc_smp_de_init(void * dm_void)1764 void adc_smp_de_init(void *dm_void)
1765 {
1766 struct dm_struct *dm = (struct dm_struct *)dm_void;
1767
1768 if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE))
1769 return;
1770
1771 phydm_la_stop(dm);
1772 phydm_la_buffer_release(dm);
1773 }
1774
1775 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
adc_smp_work_item_callback(void * context)1776 void adc_smp_work_item_callback(void *context)
1777 {
1778 void *adapter = (void *)context;
1779 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
1780 struct dm_struct *dm = &hal_data->DM_OutSrc;
1781 struct rt_adcsmp *smp = &dm->adcsmp;
1782
1783 pr_debug("[WorkItem Call back] LA_State=(%d)\n", smp->adc_smp_state);
1784 phydm_la_adc_smp_start(dm);
1785 }
1786 #endif
1787 #endif /*@endif PHYDM_LA_MODE_SUPPORT*/
1788