1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #include "mp_precomp.h"
27 #include "phydm_precomp.h"
28
29 #if (PHYDM_LA_MODE_SUPPORT)
30
31 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
32 #if (RTL8197F_SUPPORT || RTL8822B_SUPPORT || RTL8192F_SUPPORT)
33 #include "rtl8197f/Hal8197FPhyReg.h"
34 #include "WlanHAL/HalMac88XX/halmac_reg2.h"
35 #else
36 #include "WlanHAL/HalHeader/HalComReg.h"
37 #endif
38 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
39 #if WPP_SOFTWARE_TRACE
40 #include "phydm_adc_sampling.tmh"
41 #endif
42 #endif
43
44 #if RTL8814B_SUPPORT
phydm_la_finish_addr_recover_8814B(void * dm_void,u32 * finish_addr)45 boolean phydm_la_finish_addr_recover_8814B(void *dm_void, u32 *finish_addr)
46 {
47 struct dm_struct *dm = (struct dm_struct *)dm_void;
48 struct rt_adcsmp *smp = &dm->adcsmp;
49 boolean recover_success;
50
51 if (!(dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8814C)))
52 return false;
53
54 if (smp->la_buff_mode == ADCSMP_BUFF_HALF) {
55 if (*finish_addr < 0x4000) /*0~0x4000*/
56 *finish_addr += 0x8000;
57
58 recover_success = true;
59 } else {
60 if (*finish_addr >= 0x4000 && *finish_addr < 0x8000)
61 recover_success = true;
62 else
63 recover_success = false;
64 }
65 pr_debug("[8814B] recover_success=(%d)\n", recover_success);
66
67 return recover_success;
68 }
69 #endif
70
71 #if RTL8198F_SUPPORT
phydm_la_pre_run(void * dm_void)72 void phydm_la_pre_run(void *dm_void)
73 {
74 struct dm_struct *dm = (struct dm_struct *)dm_void;
75 struct rt_adcsmp *smp = &dm->adcsmp;
76 struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
77 u8 i = 0;
78 u8 tmp = 0;
79 u8 target_polling_bit = BIT(1);
80
81 if (!(dm->support_ic_type & ODM_RTL8198F))
82 return;
83
84 if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG)
85 return;
86
87 /*pre run */
88 /*force to bb trigger*/
89 odm_set_mac_reg(dm, R_0x7c0, BIT(3), 0);
90 /*dma_trig_and(AND1) output 1*/
91 odm_set_bb_reg(dm, R_0x1ce4, 0xf0000000, 0x0);
92 /*r_dma_trigger_AND1_inv = 1*/
93 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 1); /*@AND 1 val*/
94 /* polling bit for BB ADC mode */
95 odm_set_mac_reg(dm, R_0x7c0, BIT(1), 1);
96
97 pr_debug("buf[end:start]=(0x%x~0x%x)\n", buf->end_pos, buf->start_pos);
98
99 do {
100 tmp = odm_read_1byte(dm, R_0x7c0);
101 if ((tmp & target_polling_bit) == false) {
102 pr_debug("LA pre-run fail.\n");
103 phydm_la_stop(dm);
104 phydm_release_bb_dbg_port(dm);
105 } else {
106 ODM_delay_ms(100);
107 pr_debug("LA pre-run while_cnt = %d.\n", i);
108 i++;
109 }
110 } while (i < 3);
111
112 /*r_dma_trigger_AND1_inv = 0*/
113 odm_set_bb_reg(dm, R_0x1ce8, BIT5, 0); /*@AND 1 val*/
114
115 if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG)
116 odm_set_mac_reg(dm, R_0x7c0, BIT(3), 1);
117 }
118 #endif
119
120 #if (RTL8821C_SUPPORT || RTL8195B_SUPPORT)
121 void
phydm_la_clk_en(void * dm_void,boolean enable)122 phydm_la_clk_en(void *dm_void, boolean enable)
123 {
124 struct dm_struct *dm = (struct dm_struct *)dm_void;
125 u8 val = (enable) ? 1 : 0;
126
127 if (!(dm->support_ic_type & (ODM_RTL8195B | ODM_RTL8821C)))
128 return;
129
130 if (dm->support_ic_type == ODM_RTL8821C &&
131 dm->cut_version == ODM_CUT_A)
132 return;
133
134 odm_set_bb_reg(dm, R_0x95c, BIT(23), val);
135 }
136 #endif
137
138 #if (RTL8723F_SUPPORT)
139 void
phydm_la_mac_clk_en(void * dm_void,boolean enable)140 phydm_la_mac_clk_en(void *dm_void, boolean enable)
141 {
142 struct dm_struct *dm = (struct dm_struct *)dm_void;
143 u8 val = (enable) ? 1 : 0;
144
145 if (!(dm->support_ic_type & ODM_RTL8723F))
146 return;
147
148 odm_set_mac_reg(dm, R_0x1008, BIT(1), val);
149 /*Set IRAM2/3*/
150 odm_set_mac_reg(dm, R_0x1000, 0xc0, 0x0);
151 odm_set_mac_reg(dm, R_0x1000, 0x3000, 0x3);
152 }
153 #endif
154
155 #if (RTL8197F_SUPPORT)
156 void
phydm_la_stop_dma_8197f(void * dm_void,enum phydm_backup_type opt)157 phydm_la_stop_dma_8197f(void *dm_void, enum phydm_backup_type opt)
158 {
159 struct dm_struct *dm = (struct dm_struct *)dm_void;
160 struct rt_adcsmp *smp = &dm->adcsmp;
161
162 if (dm->support_ic_type != ODM_RTL8197F)
163 return;
164
165 if (opt == PHYDM_BACKUP) {
166 /*Stop DMA*/
167 smp->backup_dma = odm_get_mac_reg(dm, R_0x300, 0xffff);
168 odm_set_mac_reg(dm, R_0x300, 0x7fff, 0x7fff);
169 } else { /*restore*/
170 /*Resume DMA*/
171 odm_set_mac_reg(dm, R_0x300, 0x7fff, smp->backup_dma);
172 }
173 }
174 #endif
175
176 #ifdef PHYDM_COMPILE_LA_STORE_IN_IMEM
177 void
phydm_la_mv_data_2_tx_buffer(void * dm_void)178 phydm_la_mv_data_2_tx_buffer(void *dm_void)
179 {
180 struct dm_struct *dm = (struct dm_struct *)dm_void;
181 struct rt_adcsmp *smp = &dm->adcsmp;
182 struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
183
184 if (!(dm->support_ic_type & PHYDM_LA_STORE_IN_IMEM_IC))
185 return;
186
187 pr_debug("GetTxPktBuf from iMEM\n");
188 odm_set_mac_reg(dm, R_0x7c0, BIT(0), 0x0); /*Disable LA mode HW block*/
189
190 /* 98F LA memory loccation is separate from normal
191 * driver use, DMA is no longer required to stop
192 */
193 #if (RTL8197F_SUPPORT)
194 phydm_la_stop_dma_8197f(dm, PHYDM_BACKUP);
195 #endif
196
197 /* @move LA mode content from IMEM to TxPktBuffer
198 * Source : OCPBASE_IMEM 0x00000000
199 * Destination : OCPBASE_TXBUF 0x18780000
200 * Length : 64K
201 */
202 GET_HAL_INTERFACE(dm->priv)->init_ddma_handler(dm->priv,
203 OCPBASE_IMEM,
204 OCPBASE_TXBUF
205 + buf->start_pos,
206 0x10000);
207 }
208 #endif
209
210
211 #if(RTL8723F_SUPPORT)
212 void
phydm_la_mv_data_2_tx_buffer_rtl8723f(void * dm_void,u32 source,u32 dest,u32 length)213 phydm_la_mv_data_2_tx_buffer_rtl8723f(void *dm_void, u32 source, u32 dest, u32 length)
214 {
215 struct dm_struct *dm = (struct dm_struct *)dm_void;
216 struct rt_adcsmp *smp = &dm->adcsmp;
217 struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
218 //u32 ch0ctrl = (BIT(29)|BIT(31));
219 u32 ch0ctrl = BIT(31);
220 u32 cnt=25000;
221
222 pr_debug("GetTxPktBuf from iMEM\n");
223 /*Disable LA mode HW block*/
224 odm_set_mac_reg(dm, R_0x7c0, BIT(0), 0x0);
225
226 /* @move LA mode content from IMEM to TxPktBuffer
227 * Source : OCPBASE_IMEM 0x14040000
228 * Destination : OCPBASE_TXBUF 0x18780000
229 * Length : 32K
230 */
231 /*
232 OCPBASE_IMEM = 0x18600000;
233 OCPBASE_TXBUF = 0x18780000;
234 GET_HAL_INTERFACE(dm->priv)->init_ddma_handler(dm->priv,
235 OCPBASE_IMEM,
236 OCPBASE_TXBUF
237 + buf->start_pos,
238 0x8000);
239 */
240
241 // TODO: Replace all register define & bit define
242
243
244 //check if ddma ch0 is idle
245 while(odm_get_mac_reg(dm, R_0x1208 , BIT(31))){
246 ODM_delay_ms(10);
247 cnt--;
248 if(cnt==0){
249 pr_debug("1 InitDDMA88XX polling fail \n");
250 return;
251 }
252 }
253
254 ch0ctrl |= length & 0x3FFFF;
255
256 //check if chksum continuous
257 //ch0ctrl |= BIT(24);
258
259 odm_set_mac_reg(dm, R_0x1200, MASKDWORD, source); /*0x1200[31:0]:Source Address*/
260 odm_set_mac_reg(dm, R_0x1204, MASKDWORD, dest); /*0x1204[31:0]:Destination Address*/
261 odm_set_mac_reg(dm, R_0x1208, MASKDWORD, ch0ctrl); /*0x1208[17:0]:DMA Length*/
262 //check if ddma ch0 is idle
263 while(odm_get_mac_reg(dm, R_0x1208 , BIT(31))){
264 ODM_delay_ms(10);
265 cnt--;
266 if(cnt==0){
267 pr_debug("2 InitDDMA88XX polling fail \n");
268 return ;
269 }
270 }
271 }
272 #endif
273
274 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
275
phydm_la_bb_adv_reset_jgr3(void * dm_void)276 void phydm_la_bb_adv_reset_jgr3(void *dm_void)
277 {
278 struct dm_struct *dm = (struct dm_struct *)dm_void;
279 struct rt_adcsmp *smp = &dm->adcsmp;
280 struct la_adv_trig *adv = &smp->adv_trig_table;
281
282 odm_memory_set(dm, adv, 0, sizeof(struct la_adv_trig));
283
284 }
285
phydm_la_bb_adv_trig_setting_jgr3(void * dm_void)286 void phydm_la_bb_adv_trig_setting_jgr3(void *dm_void)
287 {
288 struct dm_struct *dm = (struct dm_struct *)dm_void;
289 struct rt_adcsmp *smp = &dm->adcsmp;
290 struct la_adv_trig *adv = &smp->adv_trig_table;
291
292 pr_debug(" *ADV BB-trig = %d\n", adv->la_adv_bbtrigger_en);
293
294 if (!adv->la_adv_bbtrigger_en) { /*normal LA mode & back to default*/
295 /*@AND0*/
296 odm_set_bb_reg(dm, R_0x1ce4, BIT(27), 0);
297
298 /*@AND1*/
299 odm_set_bb_reg(dm, R_0x1ce4, MASKH4BITS, 0);
300 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), 0); /*@AND 1 inv*/
301 /*@AND2*/
302 odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, 0);
303 odm_set_bb_reg(dm, R_0x1ce8, BIT(15), 0); /*@AND 2 inv*/
304 /*@AND3*/
305 odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, 0);
306 odm_set_bb_reg(dm, R_0x1ce8, BIT(25), 0); /*@AND 3 inv*/
307 /*@AND4*/
308 odm_set_bb_reg(dm, R_0x1cf0, MASKDWORD, 0); /*@AND 4 mask en*/
309 odm_set_bb_reg(dm, R_0x1ce8, BIT(26), 0); /*@AND 4 inv*/
310 } else {
311 /*@AND0 */
312 /*path 1 default: enable ori. BB trigger*/
313 odm_set_bb_reg(dm, R_0x1ce4, BIT(27),
314 (adv->la_ori_bb_dis ? 1 : 0));
315
316 /* @AND1 */
317 odm_set_bb_reg(dm, R_0x1ce8, BIT(5), adv->la_and1_inv);
318 odm_set_bb_reg(dm, R_0x1ce4, MASKH4BITS, adv->la_and1_sel);
319 odm_set_bb_reg(dm, R_0x1ce8, 0x1f, adv->la_and1_val);
320
321 /*@AND2 */
322 odm_set_bb_reg(dm, R_0x1ce8, BIT(15), adv->la_and2_inv);
323 odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, adv->la_and2_sel);
324 odm_set_bb_reg(dm, R_0x1ce8, 0x7c00, adv->la_and2_val);
325
326 /*@AND3 */
327 odm_set_bb_reg(dm, R_0x1ce8, BIT(25), adv->la_and3_inv);
328 odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, adv->la_and3_sel);
329 odm_set_bb_reg(dm, R_0x1ce8, 0x1f00000, adv->la_and3_val);
330
331 /*@AND4 */
332 odm_set_bb_reg(dm, R_0x1ce8, BIT(26), adv->la_and4_inv);
333 odm_set_bb_reg(dm, R_0x1cf0, MASKDWORD, adv->la_and4_mask);
334 odm_set_bb_reg(dm, R_0x1cec, MASKDWORD, adv->la_and4_bitmap);
335 }
336 }
337
phydm_la_bb_adv_cmd_show_jgr3(void * dm_void,u32 * _used,char * output,u32 * _out_len)338 void phydm_la_bb_adv_cmd_show_jgr3(void *dm_void, u32 *_used,
339 char *output, u32 *_out_len)
340 {
341 struct dm_struct *dm = (struct dm_struct *)dm_void;
342 struct rt_adcsmp *smp = &dm->adcsmp;
343 struct la_adv_trig *adv = &smp->adv_trig_table;
344
345 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
346 " *And0 Disable=%d\n", adv->la_ori_bb_dis);
347 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
348 " *And1{sel,val,inv}={0x%x,0x%x,%d}\n *And2{sel,val,inv}={0x%x,0x%x,%d}\n *And3{sel,val,inv}={0x%x,0x%x,%d}\n",
349 adv->la_and1_sel, adv->la_and1_val, adv->la_and1_inv,
350 adv->la_and2_sel, adv->la_and2_val, adv->la_and2_inv,
351 adv->la_and3_sel, adv->la_and3_val, adv->la_and3_inv);
352 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
353 " *And4{mask,bitmap,inv}={0x%x,0x%x,%d}\n",
354 adv->la_and4_mask, adv->la_and4_bitmap, adv->la_and4_inv);
355 }
356
phydm_la_bb_adv_cmd_jgr3(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)357 void phydm_la_bb_adv_cmd_jgr3(void *dm_void, char input[][16], u32 *_used,
358 char *output, u32 *_out_len)
359 {
360 struct dm_struct *dm = (struct dm_struct *)dm_void;
361 struct rt_adcsmp *smp = &dm->adcsmp;
362 struct la_adv_trig *adv = &smp->adv_trig_table;
363 u32 var1[10] = {0};
364 u32 adv_trig_en;
365
366 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
367 return;
368
369 if ((strcmp(input[2], "show") == 0)) {
370 phydm_la_bb_adv_cmd_show_jgr3(dm, _used, output, _out_len);
371 return;
372 }
373
374 PHYDM_SSCANF(input[2], DCMD_HEX, &var1[0]);
375 PHYDM_SSCANF(input[3], DCMD_HEX, &var1[1]);
376 PHYDM_SSCANF(input[4], DCMD_HEX, &var1[2]);
377 PHYDM_SSCANF(input[5], DCMD_HEX, &var1[3]);
378 PHYDM_SSCANF(input[6], DCMD_HEX, &var1[4]);
379
380 adv_trig_en = var1[0];
381
382 if (adv_trig_en != 1) {
383 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
384 "Back to Ori-BB-trig\n");
385 phydm_la_bb_adv_reset_jgr3(dm);
386 return;
387 }
388
389 adv->la_adv_bbtrigger_en = true;
390
391 if (var1[1] == 0) {
392 adv->la_ori_bb_dis = (boolean)var1[2];
393 } else if (var1[1] == 1) {
394 adv->la_and1_sel = (u8)var1[2];
395 adv->la_and1_val = (u8)var1[3];
396 adv->la_and1_inv = (boolean)var1[4];
397 } else if (var1[1] == 2) {
398 adv->la_and2_sel = (u8)var1[2];
399 adv->la_and2_val = (u8)var1[3];
400 adv->la_and2_inv = (boolean)var1[4];
401 } else if (var1[1] == 3) {
402 adv->la_and3_sel = (u8)var1[2];
403 adv->la_and3_val = (u8)var1[3];
404 adv->la_and2_inv = (boolean)var1[4];
405 } else if (var1[1] == 4) {
406 adv->la_and4_mask = var1[2];
407 adv->la_and4_bitmap = var1[3];
408 adv->la_and4_inv = (boolean)var1[4];
409 }
410
411 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
412 "[Adv_trig_en=%d]\n\n", adv_trig_en);
413
414 phydm_la_bb_adv_cmd_show_jgr3(dm, _used, output, _out_len);
415 }
416
phydm_la_cmd_fast_jgr3(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)417 void phydm_la_cmd_fast_jgr3(void *dm_void, char input[][16], u32 *_used,
418 char *output, u32 *_out_len)
419 {
420 struct dm_struct *dm = (struct dm_struct *)dm_void;
421 struct rt_adcsmp *smp = &dm->adcsmp;
422 struct la_adv_trig *adv = &smp->adv_trig_table;
423 enum auto_detection_state ad_mode;
424 const u8 ofdm_codeword[8] = {0xb, 0xf, 0xa, 0xe, 0x9, 0xd, 0x8, 0xc};
425 u32 codeword;
426 u8 rate_idx;
427 u32 trig_time_cca = 0;
428 s32 val_sign32_tmp = 0;
429 u32 var[10] = {0};
430 u8 bw = *dm->band_width;
431
432 if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES)) {
433 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
434 "Only Support for JGR-3 ICs\n");
435 return;
436 }
437
438 if (bw > 2) {
439 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
440 "Not Support for BW > %dM\n", 20 << bw);
441 return;
442 }
443
444 PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var[0]);
445 PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var[1]);
446 PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var[2]);
447
448 trig_time_cca = ((smp->smp_number_max >> (bw + 1)) / 10)
449 - (2 << (2 - bw)) - (2 - bw);
450
451 if (var[0] < 10) {
452 /*=== [Type: 0 ~ 10] : CCA P-edge trigger ==========================*/
453 /*--- Basic Trigger Setting --------------------------------*/
454 smp->la_trig_mode = 1;
455 smp->la_trig_sig_sel = 2;
456 smp->la_trigger_time = trig_time_cca;
457 smp->la_mac_mask_or_hdr_sel = 0;
458 smp->la_trigger_edge = 0;
459 smp->la_smp_rate = 2 - bw;
460 smp->la_count = 0;
461 if (var[0] == 0) { /*AGC*/
462 smp->la_dma_type = 5;
463 smp->la_dbg_port = 0x870;
464 } else if (var[0] == 1) { /*EVM*/
465 smp->la_dma_type = 4;
466 smp->la_dbg_port = 0x392;
467 } else if (var[0] == 2) { /*SNR*/
468 smp->la_dma_type = 4;
469 if (var[1] == 0)
470 smp->la_dbg_port = 0x89e;
471 else
472 smp->la_dbg_port = 0xa9e;
473 } else if (var[0] == 3) { /*CFO*/
474 smp->la_dma_type = 4;
475 if (var[1] == 0)
476 smp->la_dbg_port = 0x88c;
477 else
478 smp->la_dbg_port = 0xa8c;
479 } else if (var[0] == 4) { /*ADC*/
480 if (var[1] == 0) {
481 smp->la_dma_type = 0;
482 smp->la_dbg_port = 0x880;
483 } else {
484 smp->la_dma_type = 1;
485 smp->la_dbg_port = 0xa80;
486 }
487 }
488 /*--- Adv-Trigger Setting------------------------------------*/
489 adv->la_adv_bbtrigger_en = false;
490 } else if (var[0] < 20) {
491 /*=== [Type: 10 ~ 19]: RX-EVM Trigger ===============================*/
492 /*--- Basic Trigger Setting ---------------------------------*/
493 smp->la_trig_mode = 0;
494 smp->la_trig_sig_sel = 0;
495 smp->la_mac_mask_or_hdr_sel = 0;
496 smp->la_trigger_edge = 0;
497 smp->la_smp_rate = 2 - bw;
498 smp->la_count = 0;
499 smp->la_dma_type = 4;
500 smp->la_dbg_port = 0x392;
501
502 /*--- Adv-Trigger Setting -----------------------------------*/
503 phydm_la_bb_adv_reset_jgr3(dm);
504 adv->la_adv_bbtrigger_en = true;
505
506 /*And[0]*/
507 adv->la_ori_bb_dis = true;
508
509 /*And[1]*/
510 adv->la_and1_inv = 0;
511 adv->la_and1_sel = 4; /*RX-state*/
512 if (var[2] == 0) {
513 /*L-preamble 8+8+4 = 20*/
514 smp->la_trigger_time = trig_time_cca - 20;
515 /*Legacy Data*/
516 adv->la_and1_val = 5;
517 } else if (var[2] == 1) {
518 /*HT-preamble (8+8+4) + (8+4+4*Nrx) = 32 + Nrx * 4*/
519 smp->la_trigger_time = trig_time_cca - 32 -
520 (dm->num_rf_path * 4);
521 /*HT Data*/
522 adv->la_and1_val = 18;
523 } else {
524 /*VHT-preamble (8+8+4) + (8+4+4*Nrx) +4 = 36 + Nrx * 4*/
525 smp->la_trigger_time = trig_time_cca - 36 -
526 (dm->num_rf_path * 4);
527 /*VHT Data*/
528 adv->la_and1_val = 18;
529 }
530
531 /*And[2]*/
532 adv->la_and2_inv = 0;
533 adv->la_and2_sel = 0; /*Disable*/
534
535 /*And[3]*/
536 adv->la_and2_inv = 0;
537 adv->la_and3_sel = 0; /*Disable*/
538
539 /*And[4]*/
540 adv->la_and4_inv = 0;
541
542 if (var[0] == 11) {
543 /*[>= -X dB]*/
544 if (var[1] == 2) {
545 adv->la_and4_bitmap = 0;
546 adv->la_and4_mask = 0x1;
547 } else if (var[1] == 4) {
548 adv->la_and4_bitmap = 0;
549 adv->la_and4_mask = 0x3;
550 } else if (var[1] == 8) {
551 adv->la_and4_bitmap = 0;
552 adv->la_and4_mask = 0x7;
553 } else if (var[1] == 16) {
554 adv->la_and4_bitmap = 0;
555 adv->la_and4_mask = 0xf;
556 } else if (var[1] == 32) {
557 adv->la_and4_bitmap = 0;
558 adv->la_and4_mask = 0x1f;
559 } else if (var[1] == 64) {
560 adv->la_and4_bitmap = 0;
561 adv->la_and4_mask = 0x3f;
562 } else {
563 PDM_SNPF(*_out_len, *_used, output + *_used,
564 *_out_len - *_used,
565 "Not Support >= -%d dB\n", var[1]);
566 return;
567 }
568 } else if (var[0] == 10) {
569 /*[<= -X dB]*/
570 if (var[1] == 2) {
571 adv->la_and4_bitmap = 0x7e;
572 adv->la_and4_mask = 0x7e;
573 } else if (var[1] == 4) {
574 adv->la_and4_bitmap = 0x7c;
575 adv->la_and4_mask = 0x7c;
576 } else if (var[1] == 8) {
577 adv->la_and4_bitmap = 0x78;
578 adv->la_and4_mask = 0x78;
579 } else if (var[1] == 16) {
580 adv->la_and4_bitmap = 0x70;
581 adv->la_and4_mask = 0x70;
582 } else if (var[1] == 32) {
583 adv->la_and4_bitmap = 0x60;
584 adv->la_and4_mask = 0x60;
585 } else if (var[1] == 64) {
586 adv->la_and4_bitmap = 0x40;
587 adv->la_and4_mask = 0x40;
588 } else {
589 PDM_SNPF(*_out_len, *_used, output + *_used,
590 *_out_len - *_used,
591 "Not Support <= -%d dB\n", var[1]);
592 return;
593 }
594 } else if (var[0] == 12) {
595 /*[= -X dB]*/
596 val_sign32_tmp = 0 - (s32)var[1];
597 adv->la_and4_bitmap = (u32)(val_sign32_tmp & 0x7f);
598 adv->la_and4_mask = 0x7f;
599 }
600 } else if (var[0] < 30) {
601 /*=== [Type: 20 ~ 29]: RX-Rate Trigger ==============================*/
602 /*--- Basic Trigger Setting ---------------------------------*/
603 smp->la_trig_mode = 0;
604 smp->la_trig_sig_sel = 0;
605 smp->la_mac_mask_or_hdr_sel = 0;
606 smp->la_trigger_edge = 0;
607 smp->la_smp_rate = 2 - bw;
608 smp->la_count = 0;
609 smp->la_dma_type = 4;
610
611 rate_idx = (u8)var[1];
612
613 /*--- Adv-Trigger Setting -----------------------------------*/
614 phydm_la_bb_adv_reset_jgr3(dm);
615 adv->la_adv_bbtrigger_en = true;
616
617 /*And[0]*/
618 adv->la_ori_bb_dis = true;
619
620 /*And[1]*/
621 adv->la_and1_inv = 0;
622 adv->la_and1_sel = 4; /*RX-state*/
623
624 if (rate_idx <= ODM_RATE54M && rate_idx >= ODM_RATE6M) {
625 ad_mode = AD_LEGACY_MODE;
626 codeword = (u32)ofdm_codeword[rate_idx - ODM_RATE6M];
627 smp->la_dbg_port = 0x3a9;
628 /*L-preamble 8+8 = 16*/
629 smp->la_trigger_time = trig_time_cca - 20;
630 /*Legacy Data*/
631 adv->la_and1_val = 5;
632 } else if (rate_idx <= ODM_RATEMCS31) {
633 ad_mode = AD_HT_MODE;
634 codeword = (u32)(rate_idx - ODM_RATEMCS0);
635 smp->la_dbg_port = 0x3aa;
636 /*HT-preamble (8+8+4) + (8+4+4*Nrx) = 32 + Nrx * 4*/
637 smp->la_trigger_time = trig_time_cca - 32 -
638 (dm->num_rf_path * 4);
639 /*HT,VHT Data*/
640 adv->la_and1_val = 18;
641 } else if (rate_idx <= ODM_RATEVHTSS4MCS9) {
642 ad_mode = AD_VHT_MODE;
643 codeword = (u32)phydm_rate_order_compute(dm, rate_idx);
644 codeword--;
645 smp->la_dbg_port = 0x3ab;
646 /*VHT-preamble (8+8+4) + (8+4+4*Nrx) = 36 + Nrx * 4*/
647 smp->la_trigger_time = trig_time_cca - 36 -
648 (dm->num_rf_path * 4);
649 /*HT,VHT Data*/
650 adv->la_and1_val = 18;
651 } else {
652 PDM_SNPF(*_out_len, *_used, output + *_used,
653 *_out_len - *_used,
654 "Not Support\n");
655 return;
656 }
657
658 /*And[2]*/
659 adv->la_and2_inv = 0;
660 adv->la_and2_sel = 0; /*Disable*/
661
662 /*And[3]*/
663 adv->la_and2_inv = 0;
664 adv->la_and3_sel = 0; /*Disable*/
665
666 /*And[4]*/
667 adv->la_and4_inv = 0;
668
669 if (var[0] == 20) {
670 if (ad_mode == AD_LEGACY_MODE) {
671 adv->la_and4_bitmap = codeword;
672 adv->la_and4_mask = 0x3000000f;
673 } else if (ad_mode == AD_HT_MODE) {
674 adv->la_and4_bitmap = (2 << 28) | codeword;
675 adv->la_and4_mask = 0x3000003f;
676 } else { /* AD_VHT_MODE*/
677 adv->la_and4_bitmap = (1 << 28) |
678 (codeword << 4);
679 adv->la_and4_mask = 0x300000f0;
680 }
681 } else {
682 PDM_SNPF(*_out_len, *_used, output + *_used,
683 *_out_len - *_used,
684 "Not Support\n");
685 return;
686 }
687 } else {
688 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
689 "Not Support\n");
690 return;
691 }
692 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
693 "[Basic-Trigger]\n");
694 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
695 " *echo lamode 1 %d %d %d %d %d %x %d %d %d\n\n",
696 smp->la_trig_mode, smp->la_trig_sig_sel, smp->la_dma_type,
697 smp->la_trigger_time, smp->la_mac_mask_or_hdr_sel,
698 smp->la_dbg_port, smp->la_trigger_edge, smp->la_smp_rate,
699 smp->la_count);
700 pr_debug("echo lamode 1 %d %d %d %d %d %x %d %d %d\n\n",
701 smp->la_trig_mode, smp->la_trig_sig_sel, smp->la_dma_type,
702 smp->la_trigger_time, smp->la_mac_mask_or_hdr_sel,
703 smp->la_dbg_port, smp->la_trigger_edge, smp->la_smp_rate,
704 smp->la_count);
705
706 if (adv->la_adv_bbtrigger_en) {
707 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
708 "[Adv-Trigger]\n");
709 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
710 " *And0 Disable=%d\n", adv->la_ori_bb_dis);
711 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
712 " *And1{sel,val,inv}={0x%x,0x%x,%d}\n *And2{sel,val,inv}={0x%x,0x%x,%d}\n *And3{sel,val,inv}={0x%x,0x%x,%d}\n",
713 adv->la_and1_sel, adv->la_and1_val, adv->la_and1_inv,
714 adv->la_and2_sel, adv->la_and2_val, adv->la_and2_inv,
715 adv->la_and3_sel, adv->la_and3_val, adv->la_and3_inv);
716 PDM_SNPF(*_out_len, *_used, output + *_used, *_out_len - *_used,
717 " *And4{mask,bitmap,inv}={0x%x,0x%x,%d}\n",
718 adv->la_and4_mask, adv->la_and4_bitmap,
719 adv->la_and4_inv);
720 }
721 phydm_la_set(dm);
722 }
723
724 #endif
725
726 void
phydm_la_buffer_print(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)727 phydm_la_buffer_print(void *dm_void, char input[][16], u32 *_used,
728 char *output, u32 *_out_len)
729 {
730 struct dm_struct *dm = (struct dm_struct *)dm_void;
731 struct rt_adcsmp *smp = &dm->adcsmp;
732 struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
733 u64 la_pattern_msb, la_pattern_lsb;
734 u64 la_pattern, la_pattern_part;
735 s64 tmp_s64;
736 u64 mask = 0xffffffff;
737 u8 mask_length = 0;
738 u32 i;
739 u32 idx;
740 u32 var[10] = {0};
741
742 if (!buf->octet || buf->length == 0 || buf->length < smp->smp_number)
743 return;
744
745 PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var[0]);
746 PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var[1]);
747 PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var[2]);
748 PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var[3]);
749
750 pr_debug("echo lamode 1 %d %d %d %d %d %x %d %d %d\n\n",
751 smp->la_trig_mode, smp->la_trig_sig_sel, smp->la_dma_type,
752 smp->la_trigger_time, smp->la_mac_mask_or_hdr_sel,
753 smp->la_dbg_port, smp->la_trigger_edge, smp->la_smp_rate,
754 smp->la_count);
755 pr_debug("[LA Data Dump] smp_number = %d\n", smp->smp_number);
756 pr_debug("Dump_Start\n");
757
758 if (var[0] == 0) {
759 for (i = 0; i < smp->smp_number; i++) {
760 idx = i << 1;
761 pr_debug("%08x%08x\n", buf->octet[idx],
762 buf->octet[idx + 1]);
763 }
764 } else if (var[0] == 1) {
765 /*------------------------*/
766 if (var[1] == 0)
767 pr_debug("[Hex]\n");
768 else if (var[1] == 1)
769 pr_debug("[Dec unsigned]\n");
770 else if (var[1] == 2)
771 pr_debug("[Dec signed]\n");
772
773 pr_debug("BIT[%d:%d]\n", var[3], var[2]);
774
775 if (var[2] > var[3]) {
776 pr_debug("[Warning] BIT_L > BIT_H\n");
777 return;
778 }
779
780 mask_length = (u8)(var[3] - var[2] + 1);
781 mask = phydm_gen_bitmask(mask_length) << var[2];
782 /*------------------------*/
783 for (i = 0; i < smp->smp_number; i++) {
784 idx = i << 1;
785 la_pattern_msb = (u64)buf->octet[idx];
786 la_pattern_lsb = (u64)buf->octet[idx + 1];
787 la_pattern = (la_pattern_msb << 32) | la_pattern_lsb;
788 la_pattern_part = (la_pattern & mask) >> var[2];
789
790 if (var[1] == 0) {
791 pr_debug("0x%llx\n", la_pattern_part);
792 } else if (var[1] == 1) {
793 pr_debug("%llu\n", la_pattern_part);
794 } else if (var[1] == 2) {
795 tmp_s64 = phydm_cnvrt_2_sign_64(la_pattern_part,
796 mask_length);
797 pr_debug("%lld\n", tmp_s64);
798 }
799 }
800 }
801 pr_debug("Dump_End\n\n");
802 }
803
804 void
phydm_la_buffer_release(void * dm_void)805 phydm_la_buffer_release(void *dm_void)
806 {
807 struct dm_struct *dm = (struct dm_struct *)dm_void;
808 struct rt_adcsmp *smp = &dm->adcsmp;
809 struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
810
811 if (buf->length != 0x0) {
812 odm_free_memory(dm, buf->octet, buf->length);
813 buf->length = 0x0;
814 }
815 }
816
817 boolean
phydm_la_buffer_allocate(void * dm_void)818 phydm_la_buffer_allocate(void *dm_void)
819 {
820 struct dm_struct *dm = (struct dm_struct *)dm_void;
821 struct rt_adcsmp *smp = &dm->adcsmp;
822 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
823 void *adapter = dm->adapter;
824 #endif
825 struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
826 boolean ret = true;
827
828 pr_debug("[LA mode BufferAllocate]\n");
829
830 if (buf->length == 0) {
831 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
832 if (PlatformAllocateMemoryWithZero(adapter, (void **)&
833 buf->octet,
834 buf->buffer_size) !=
835 RT_STATUS_SUCCESS)
836 ret = false;
837 #else
838 odm_allocate_memory(dm, (void **)&buf->octet, buf->buffer_size);
839
840 if (!buf->octet)
841 ret = false;
842 #endif
843
844 if (ret)
845 buf->length = buf->buffer_size;
846 }
847
848 return ret;
849 }
850
phydm_la_access_tx_pkt_buf(void * dm_void,u32 addr,u32 buff_idx)851 void phydm_la_access_tx_pkt_buf(void *dm_void, u32 addr, u32 buff_idx)
852 {
853 struct dm_struct *dm = (struct dm_struct *)dm_void;
854 struct rt_adcsmp *smp = &dm->adcsmp;
855 struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
856 u32 page;
857 u32 data_l = 0, data_h = 0;
858
859 #if (RTL8192F_SUPPORT)
860 if (dm->support_ic_type & ODM_RTL8192F) {
861 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
862 indirect_access_sdram_8192f(dm->adapter, TX_PACKET_BUFFER,
863 TRUE, (u16)addr >> 3, 0,
864 &data_h, &data_l);
865 #else
866 odm_write_1byte(dm, R_0x0106, 0x69);
867 odm_set_mac_reg(dm, R_0x0140, MASKDWORD, addr >> 3);
868 data_l = odm_get_mac_reg(dm, R_0x0144, MASKDWORD);
869 data_h = odm_get_mac_reg(dm, R_0x0148, MASKDWORD);
870 odm_write_1byte(dm, R_0x0106, 0x0);
871 #endif
872 } else
873 #endif
874 {
875 /* Reg140=0x780+(addr>>12),
876 * addr=0x30~0x3F, total 16 pages
877 */
878 page = addr >> 12;
879
880 if (page != smp->txff_page) {
881 smp->txff_page = page;
882 odm_set_mac_reg(dm, R_0x0140, MASKLWORD, 0x780 + page);
883 }
884 data_l = odm_read_4byte(dm, R_0x8000 + (addr & 0xfff));
885 data_h = odm_read_4byte(dm, R_0x8000 + (addr & 0xfff) + 4);
886 }
887
888 buf->octet[buff_idx] = data_h;
889 buf->octet[buff_idx + 1] = data_l;
890
891 /*@==== [Print LA Patterns] ==========================================*/
892 if (smp->is_la_print)
893 pr_debug("%08x%08x\n", data_h, data_l);
894 }
895
phydm_la_get_tx_pkt_buf(void * dm_void)896 void phydm_la_get_tx_pkt_buf(void *dm_void)
897 {
898 struct dm_struct *dm = (struct dm_struct *)dm_void;
899 struct rt_adcsmp *smp = &dm->adcsmp;
900 struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
901 u32 i = 0, value32 = 0;
902 u32 addr = 0, finish_addr = 0; /* @(unit: 8Byte)*/
903 boolean is_round_up = false;
904 u32 addr_8byte = 0;
905 u32 round_up_point = 0;
906 u32 index = 0;
907 u32 imem_base;
908 u32 txbuf_base;
909 u32 dma_len;
910 u32 imem_start_addr;
911 u32 imem_start_addr_offset;
912 u32 txbuff_start_addr;
913 u32 tx_buff_addr;
914
915 #if (RTL8814B_SUPPORT)
916 boolean recover_success = true;
917 #endif
918
919 odm_memory_set(dm, buf->octet, 0, buf->length);
920 pr_debug("GetTxPktBuf\n");
921
922 /*@==== [Get LA Report] ==============================================*/
923 if (dm->support_ic_type & ODM_RTL8192F) {
924 value32 = odm_read_4byte(dm, R_0x7f0);
925 is_round_up = (boolean)((value32 & BIT(31)) >> 31);
926 finish_addr = (value32 & 0x7FFF8000) >> 15; /*@16 bit (unit: 8Byte)*/
927 } else {
928 odm_write_1byte(dm, R_0x0106, 0x69);
929 value32 = odm_read_4byte(dm, R_0x7c0);
930 is_round_up = (boolean)((value32 & BIT(31)) >> 31);
931
932 if (dm->support_ic_type & PHYDM_LA_STORE_IN_IMEM_IC)
933 finish_addr = (value32 & 0x7FFF8000) >> 15; /*@16 bit (unit: 8Byte)*/
934 else
935 finish_addr = (value32 & 0x7FFF0000) >> 16; /*@15bit (unit: 8Byte)*/
936 }
937
938 #if (RTL8814B_SUPPORT)
939 recover_success = phydm_la_finish_addr_recover_8814B(dm, &finish_addr);
940 #endif
941
942 pr_debug("start_addr = ((0x%x)), end_addr = ((0x%x)), buffer_size = ((0x%x))\n",
943 buf->start_pos, buf->end_pos, buf->buffer_size);
944 if (is_round_up) {
945 pr_debug("buf_start(0x%x)|----2---->|finish_addr(0x%x)|----1---->|buf_end(0x%x)\n",
946 buf->start_pos, finish_addr << 3, buf->end_pos);
947 addr = (finish_addr + 2) << 3; /*+1 or +2 ??*/
948 round_up_point = (buf->end_pos - addr) >> 3; /*@Byte to 8Byte*/
949 smp->smp_number = smp->smp_number_max;
950 pr_debug("is_round_up=(%d), round_up_point=(%d), 0x7c0/0x7F0=(0x%x), smp_number=(%d)\n",
951 is_round_up, round_up_point, value32, smp->smp_number);
952 } else {
953 pr_debug("buf_start(0x%x)|------->|finish_addr(0x%x) |buf_end(0x%x)\n",
954 buf->start_pos, finish_addr << 3, buf->end_pos);
955 addr = buf->start_pos;
956 addr_8byte = addr >> 3;
957 smp->smp_number = DIFF_2(addr_8byte, finish_addr);
958
959 pr_debug("is_round_up=(%d), smp_number=(%d)\n",
960 is_round_up, smp->smp_number);
961 }
962
963 /*@==== [Get LA Patterns in TXFF] ====================================*/
964 pr_debug("Dump_Start\n");
965 #if(RTL8723F_SUPPORT)
966 imem_base = 0x14040000;
967 txbuf_base = 0x18780000;
968 dma_len = 0x8000;
969 txbuff_start_addr = txbuf_base;
970 imem_start_addr_offset = addr;
971 if (is_round_up) {
972 for(index = 0;index < 4;index++) {
973 dma_len = 0x8000;
974 imem_start_addr= imem_base + (imem_start_addr_offset&0x1FFFF);
975
976 if((imem_start_addr_offset + 0x8000) >= buf->end_pos) {
977 dma_len = buf->end_pos-imem_start_addr_offset;
978
979 phydm_la_mv_data_2_tx_buffer_rtl8723f(dm, imem_start_addr, txbuff_start_addr, dma_len);
980
981 tx_buff_addr = 0;
982 for (i = 0; i < (dma_len >> 3); i++) {
983 phydm_la_access_tx_pkt_buf(dm, tx_buff_addr, i << 1);
984 tx_buff_addr += 8;
985 }
986 imem_start_addr = imem_base;
987 dma_len = 0x8000-dma_len;
988 phydm_la_mv_data_2_tx_buffer_rtl8723f(dm, imem_start_addr, txbuff_start_addr, dma_len);
989
990 tx_buff_addr = 0;
991 for (i = 0; i < (dma_len >> 3); i++) {
992 phydm_la_access_tx_pkt_buf(dm, tx_buff_addr, i << 1);
993 tx_buff_addr += 8;
994 }
995 imem_start_addr_offset = dma_len;
996 }
997 else {
998 dma_len = 0x8000;
999 phydm_la_mv_data_2_tx_buffer_rtl8723f(dm, imem_start_addr, txbuff_start_addr, dma_len);
1000
1001 tx_buff_addr = 0;
1002 for (i = 0; i <4096; i++) {
1003 phydm_la_access_tx_pkt_buf(dm, tx_buff_addr, i << 1);
1004 tx_buff_addr += 8;
1005 }
1006 imem_start_addr_offset += 0x8000;
1007 }
1008 }
1009 } else {
1010 for(index = 0; index < 4;index++) {
1011 imem_start_addr = imem_base + (imem_start_addr_offset & 0x1FFFF);
1012 if ((imem_start_addr_offset + 0x8000) > (finish_addr << 3))
1013 dma_len = (finish_addr << 3) - imem_start_addr_offset; /*0x1208[17:0]:DMA Length*/
1014 phydm_la_mv_data_2_tx_buffer_rtl8723f(dm,imem_start_addr, txbuff_start_addr, dma_len);
1015 tx_buff_addr = 0;
1016 for (i = 0; i < (dma_len >> 3); i++) {
1017 phydm_la_access_tx_pkt_buf(dm, tx_buff_addr, i << 1);
1018 tx_buff_addr += 8;
1019 }
1020 dma_len = 0x8000;
1021 imem_start_addr_offset += 0x8000;
1022 if (imem_start_addr_offset > (finish_addr << 3))
1023 break;
1024 }
1025 }
1026 #else
1027
1028 #ifdef PHYDM_COMPILE_LA_STORE_IN_IMEM
1029 phydm_la_mv_data_2_tx_buffer(dm);
1030 #endif
1031
1032 #if (RTL8814B_SUPPORT)
1033 if ((dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8814C)) &&
1034 !recover_success) {
1035 addr = buf->start_pos;
1036 smp->smp_number = smp->smp_number_max;
1037 }
1038 #endif
1039
1040 for (i = 0; i < smp->smp_number; i++) {
1041 phydm_la_access_tx_pkt_buf(dm, addr, i << 1);
1042 addr += 8;
1043
1044 if (addr >= buf->end_pos)
1045 addr = buf->start_pos; /*Ring buffer*/
1046 }
1047
1048 #if (RTL8197F_SUPPORT)
1049 phydm_la_stop_dma_8197f(dm, PHYDM_RESTORE);
1050 #endif
1051 #endif
1052 pr_debug("Dump_End\n");
1053 }
1054
phydm_la_set_trig_src(void * dm_void,u8 la_trig_mode)1055 void phydm_la_set_trig_src(void *dm_void, u8 la_trig_mode)
1056 {
1057 struct dm_struct *dm = (struct dm_struct *)dm_void;
1058 u32 reg = (dm->support_ic_type == ODM_RTL8192F) ? R_0x7f0 : R_0x7c0;
1059
1060 if (la_trig_mode == PHYDM_ADC_MAC_TRIG)
1061 odm_set_mac_reg(dm, reg, BIT(3), 1);
1062 else
1063 odm_set_mac_reg(dm, reg, BIT(3), 0);
1064 }
1065
phydm_la_set_mac_iq_dump(void * dm_void,boolean impossible_trig_condi)1066 void phydm_la_set_mac_iq_dump(void *dm_void, boolean impossible_trig_condi)
1067 {
1068 struct dm_struct *dm = (struct dm_struct *)dm_void;
1069 struct rt_adcsmp *smp = &dm->adcsmp;
1070 u32 reg_value = 0;
1071 u32 reg1 = 0, reg2 = 0, reg3 = 0;
1072
1073 if (dm->support_ic_type & ODM_RTL8192F) {
1074 reg1 = R_0x7f0;
1075 reg2 = R_0x7f4;
1076 reg3 = R_0x7f8;
1077 } else {
1078 reg1 = R_0x7c0;
1079 reg2 = R_0x7c4;
1080 reg3 = R_0x7c8;
1081 }
1082
1083 odm_write_1byte(dm, reg1, 0); /*@clear all reg1*/
1084 /*@Enable LA mode HW block*/
1085 odm_set_mac_reg(dm, reg1, BIT(0), 1);
1086
1087 #if (RTL8723F_SUPPORT)
1088 if (dm->support_ic_type & ODM_RTL8723F)
1089 phydm_la_mac_clk_en(dm, true);
1090 #endif
1091
1092 if (smp->la_trig_mode == PHYDM_MAC_TRIG) {
1093 smp->la_dump_mode = LA_MAC_DBG_DUMP;
1094 /*polling bit for MAC mode*/
1095 odm_set_mac_reg(dm, reg1, BIT(2), 1);
1096 /*trigger mode for MAC*/
1097 odm_set_mac_reg(dm, reg1, 0x18, smp->la_trigger_edge);
1098 pr_debug("[MAC_trig] ref_mask=(0x%x), ref_value=(0x%x), dbg_port =(0x%x)\n",
1099 smp->la_mac_mask_or_hdr_sel, smp->la_trig_sig_sel,
1100 smp->la_dbg_port);
1101 /*@[Set MAC Debug Port]*/
1102 odm_set_mac_reg(dm, R_0xf4, BIT(16), 1);
1103 odm_set_mac_reg(dm, R_0x38, 0xff0000, smp->la_dbg_port);
1104 odm_set_mac_reg(dm, reg2, MASKDWORD,
1105 smp->la_mac_mask_or_hdr_sel);
1106 odm_set_mac_reg(dm, reg3, MASKDWORD, smp->la_trig_sig_sel);
1107 } else {
1108 smp->la_dump_mode = LA_BB_ADC_DUMP;
1109
1110 if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) {
1111 /*polling bit for MAC trigger event*/
1112 if (impossible_trig_condi)
1113 phydm_la_set_trig_src(dm, PHYDM_ADC_BB_TRIG);
1114 else
1115 phydm_la_set_trig_src(dm, PHYDM_ADC_MAC_TRIG);
1116
1117 odm_set_mac_reg(dm, reg1, 0xc0, smp->la_trig_sig_sel);
1118
1119 if (smp->la_trig_sig_sel == ADCSMP_TRIG_REG) {
1120 /* @manual trigger reg1[5] = 0->1*/
1121 odm_set_mac_reg(dm, reg1, BIT(5), 1);
1122 }
1123 }
1124 /*polling bit for BB ADC mode*/
1125 odm_set_mac_reg(dm, reg1, BIT(1), 1);
1126 }
1127
1128 reg_value = odm_get_mac_reg(dm, reg1, 0xff);
1129 pr_debug("4. [Set MAC IQ dump] 0x%x[7:0]=(0x%x)\n", reg1, reg_value);
1130
1131 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1132 RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
1133 ("4. [Set MAC IQ dump] 0x%x[7:0]=(0x%x)\n", reg1,
1134 reg_value));
1135 #endif
1136 }
1137
phydm_la_set_bb_dbg_port(void * dm_void,boolean impossible_trig_condi)1138 void phydm_la_set_bb_dbg_port(void *dm_void, boolean impossible_trig_condi)
1139 {
1140 struct dm_struct *dm = (struct dm_struct *)dm_void;
1141 struct rt_adcsmp *smp = &dm->adcsmp;
1142
1143 u8 trig_mode = smp->la_trig_mode;
1144 u32 trig_sel = smp->la_trig_sig_sel;
1145 u32 dbg_port = smp->la_dbg_port;
1146
1147 if (trig_mode == PHYDM_MAC_TRIG)
1148 trig_sel = 0; /*@ignore this setting*/
1149
1150 /*set BB debug port*/
1151 if (impossible_trig_condi) {
1152 dbg_port = 0xf;
1153 trig_sel = 0;
1154 pr_debug("[BB Setting] fake-trigger!\n");
1155 }
1156
1157 if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbg_port)) {
1158 pr_debug(" *Set dbg_port=(0x%x)\n", dbg_port);
1159 } else {
1160 dbg_port = phydm_get_bb_dbg_port_idx(dm);
1161 pr_debug("[Set dbg_port fail!] Curr-DbgPort=0x%x\n", dbg_port);
1162 }
1163
1164 /*@debug port bit*/
1165 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
1166 odm_set_bb_reg(dm, R_0x95c, 0x1f, trig_sel);
1167 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
1168 } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1169 odm_set_bb_reg(dm, R_0x1ce4, 0x3e000, trig_sel);
1170 #endif
1171 } else {
1172 odm_set_bb_reg(dm, R_0x9a0, 0x1f, trig_sel);
1173 }
1174
1175 if (smp->la_trig_mode == PHYDM_ADC_BB_TRIG) {
1176 pr_debug(" *Set dbg_port[BIT] = %d\n", trig_sel);
1177
1178 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1179 RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
1180 (" *Set dbg_port[BIT] = %d\n", trig_sel));
1181 #endif
1182 }
1183 }
1184
phydm_la_set_bb(void * dm_void)1185 void phydm_la_set_bb(void *dm_void)
1186 {
1187 struct dm_struct *dm = (struct dm_struct *)dm_void;
1188 struct rt_adcsmp *smp = &dm->adcsmp;
1189
1190 u8 trig_mode = smp->la_trig_mode;
1191 u8 edge = smp->la_trigger_edge;
1192 u8 smp_rate = smp->la_smp_rate;
1193 u8 dma_type = smp->la_dma_type;
1194 u32 dbg_port_hdr_sel = 0;
1195 char *trig_mode_word = NULL;
1196
1197 pr_debug("3. [BB Setting] mode=(%d), Edge=(%s), smp_rate=(%dM), Dma_type=(%d)\n",
1198 trig_mode,
1199 (edge == 0) ? "P" : "N", 80 >> smp_rate, dma_type);
1200
1201 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
1202 if (trig_mode == PHYDM_ADC_RF0_TRIG)
1203 dbg_port_hdr_sel = 9; /*@DBGOUT_RFC_a[31:0]*/
1204 else if (trig_mode == PHYDM_ADC_RF1_TRIG)
1205 dbg_port_hdr_sel = 8; /*@DBGOUT_RFC_b[31:0]*/
1206 else if ((trig_mode == PHYDM_ADC_BB_TRIG) ||
1207 (trig_mode == PHYDM_ADC_MAC_TRIG)) {
1208 if (smp->la_mac_mask_or_hdr_sel <= 0xf)
1209 dbg_port_hdr_sel = smp->la_mac_mask_or_hdr_sel;
1210 else
1211 dbg_port_hdr_sel = 0;
1212 }
1213
1214 phydm_bb_dbg_port_header_sel(dm, dbg_port_hdr_sel);
1215
1216 odm_set_bb_reg(dm, R_0x8b4, BIT(7), 1);/*@update rpt every pkt*/
1217 odm_set_bb_reg(dm, R_0x95c, 0xf00, dma_type);
1218 /*@0: posedge, 1: negedge*/
1219 odm_set_bb_reg(dm, R_0x95c, BIT(31), edge);
1220 odm_set_bb_reg(dm, R_0x95c, 0xe0, smp_rate);
1221 /* @(0:) '80MHz'
1222 * (1:) '40MHz'
1223 * (2:) '20MHz'
1224 * (3:) '10MHz'
1225 * (4:) '5MHz'
1226 * (5:) '2.5MHz'
1227 * (6:) '1.25MHz'
1228 * (7:) '160MHz (for BW160 ic)'
1229 */
1230 #if (RTL8821C_SUPPORT || RTL8195B_SUPPORT)
1231 phydm_la_clk_en(dm, true);
1232 #endif
1233
1234 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
1235 } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1236 odm_set_bb_reg(dm, R_0x1eb4, BIT(23), 0x1);/*@update rpt every pkt*/
1237 /*@MAC-PHY timing*/
1238 odm_set_bb_reg(dm, R_0x1ce4, BIT(7) | BIT(6), 0);
1239 odm_set_bb_reg(dm, R_0x1cf4, BIT(23), 1); /*@LA mode on*/
1240 odm_set_bb_reg(dm, R_0x1ce4, 0x3f, dma_type);
1241 /*@0: posedge, 1: negedge ??*/
1242 odm_set_bb_reg(dm, R_0x1ce4, BIT(26), edge);
1243 odm_set_bb_reg(dm, R_0x1ce4, 0x700, smp_rate);
1244
1245 phydm_la_bb_adv_trig_setting_jgr3(dm);
1246 #endif
1247 } else {
1248 if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
1249 odm_set_bb_reg(dm, R_0xd00, BIT(26), 0x1); /*@update rpt every pkt*/
1250
1251 #if (RTL8192F_SUPPORT)
1252 if ((dm->support_ic_type & ODM_RTL8192F))
1253 /*@LA reset HW block enable for true-mac asic*/
1254 odm_set_bb_reg(dm, R_0x9a0, BIT(15), 1);
1255 #endif
1256
1257 odm_set_bb_reg(dm, R_0x9a0, 0xf00, dma_type);
1258 /*@0: posedge, 1: negedge*/
1259 odm_set_bb_reg(dm, R_0x9a0, BIT(31), edge);
1260 odm_set_bb_reg(dm, R_0x9a0, 0xe0, smp_rate);
1261 /* @(0:) '80MHz'
1262 * (1:) '40MHz'
1263 * (2:) '20MHz'
1264 * (3:) '10MHz'
1265 * (4:) '5MHz'
1266 * (5:) '2.5MHz'
1267 * (6:) '1.25MHz'
1268 * (7:) '160MHz (for BW160 ic)'
1269 */
1270 }
1271 }
1272
phydm_la_set_mac_trigger_time(void * dm_void,u32 trigger_time_mu_sec)1273 void phydm_la_set_mac_trigger_time(void *dm_void, u32 trigger_time_mu_sec)
1274 {
1275 struct dm_struct *dm = (struct dm_struct *)dm_void;
1276 u8 time_unit_num = 0;
1277 u32 unit = 0;
1278
1279 if (trigger_time_mu_sec < 128)
1280 unit = 0; /*unit: 1mu sec*/
1281 else if (trigger_time_mu_sec < 256)
1282 unit = 1; /*unit: 2mu sec*/
1283 else if (trigger_time_mu_sec < 512)
1284 unit = 2; /*unit: 4mu sec*/
1285 else if (trigger_time_mu_sec < 1024)
1286 unit = 3; /*unit: 8mu sec*/
1287 else if (trigger_time_mu_sec < 2048)
1288 unit = 4; /*unit: 16mu sec*/
1289 else if (trigger_time_mu_sec < 4096)
1290 unit = 5; /*unit: 32mu sec*/
1291 else if (trigger_time_mu_sec < 8192)
1292 unit = 6; /*unit: 64mu sec*/
1293 else if (trigger_time_mu_sec < 16384)
1294 if (dm->support_ic_type & ODM_RTL8723F)
1295 unit = 7; /*unit: 128mu sec*/
1296
1297 time_unit_num = (u8)(trigger_time_mu_sec >> unit);
1298
1299 pr_debug("2. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n",
1300 time_unit_num, unit);
1301 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1302 RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, (
1303 "3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n",
1304 time_unit_num, unit));
1305 #endif
1306
1307 if (dm->support_ic_type & ODM_RTL8192F) {
1308 odm_set_mac_reg(dm, R_0x7fc, BIT(2) | BIT(1) | BIT(0), unit);
1309 odm_set_mac_reg(dm, R_0x7f0, 0x7f00, (time_unit_num & 0x7f));
1310 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
1311 } else if (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8814C)) {
1312 odm_set_mac_reg(dm, R_0x7cc, BIT(20) | BIT(19) | BIT(18), unit);
1313 odm_set_mac_reg(dm, R_0x7c0, 0x7f00, (time_unit_num & 0x7f));
1314 } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1315 odm_set_mac_reg(dm, R_0x7cc, BIT(18) | BIT(17) | BIT(16), unit);
1316 odm_set_mac_reg(dm, R_0x7c0, 0x7f00, (time_unit_num & 0x7f));
1317 #endif
1318 } else {
1319 odm_set_mac_reg(dm, R_0x7cc, BIT(20) | BIT(19) | BIT(18), unit);
1320 odm_set_mac_reg(dm, R_0x7c0, 0x7f00, (time_unit_num & 0x7f));
1321 }
1322 }
1323
phydm_la_set_buff_mode(void * dm_void,enum la_buff_mode mode)1324 void phydm_la_set_buff_mode(void *dm_void, enum la_buff_mode mode)
1325 {
1326 struct dm_struct *dm = (struct dm_struct *)dm_void;
1327 struct rt_adcsmp *smp = &dm->adcsmp;
1328 struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
1329 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
1330 struct rtl8192cd_priv *priv = dm->priv;
1331 u8 normal_LA_on = priv->pmib->miscEntry.normal_LA_on;
1332 #endif
1333 u32 buff_size_base = 0;
1334 u32 end_pos_tmp = 0;
1335
1336 smp->la_buff_mode = mode;
1337 switch (dm->support_ic_type) {
1338 case ODM_RTL8814A:
1339 buff_size_base = 0x10000;
1340 end_pos_tmp = 0x40000;
1341 break;
1342 case ODM_RTL8822B:
1343 case ODM_RTL8822C:
1344 case ODM_RTL8812F:
1345 buff_size_base = 0x20000; /*@WIN: TX_FIFO_SIZE_LA_8822C*/
1346 end_pos_tmp = 0x40000;
1347 break;
1348 case ODM_RTL8814B:
1349 case ODM_RTL8814C:
1350 buff_size_base = 0x30000;
1351 end_pos_tmp = 0x60000;
1352 break;
1353 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
1354 case ODM_RTL8197F:
1355 case ODM_RTL8198F:
1356 case ODM_RTL8197G:
1357 buff_size_base = 0x10000;
1358 end_pos_tmp = (normal_LA_on == 1) ? 0x20000 : 0x10000;
1359 break;
1360 #endif
1361 case ODM_RTL8192F:
1362 buff_size_base = 0xE000;
1363 end_pos_tmp = 0x10000;
1364 break;
1365 case ODM_RTL8821C:
1366 buff_size_base = 0x8000;
1367 end_pos_tmp = 0x10000;
1368 break;
1369 case ODM_RTL8195B:
1370 buff_size_base = 0x4000;
1371 end_pos_tmp = 0x8000;
1372 break;
1373 case ODM_RTL8723F:
1374 buff_size_base = 0x20000;
1375 end_pos_tmp = 0x20000;
1376 break;
1377 default:
1378 pr_debug("[%s] Warning!", __func__);
1379 break;
1380 }
1381
1382 buf->buffer_size = buff_size_base;
1383
1384 if (dm->support_ic_type & (ODM_RTL8814B | ODM_RTL8814C)) {
1385 if (mode == ADCSMP_BUFF_HALF) {
1386 odm_set_mac_reg(dm, R_0x7cc, BIT(21), 0);
1387 } else {
1388 buf->buffer_size = buf->buffer_size << 1;
1389 odm_set_mac_reg(dm, R_0x7cc, BIT(21), 1);
1390 }
1391 } else if (dm->support_ic_type & FULL_BUFF_MODE_SUPPORT) {
1392 if (mode == ADCSMP_BUFF_HALF) {
1393 odm_set_mac_reg(dm, R_0x7cc, BIT(30), 0);
1394 } else {
1395 buf->buffer_size = buf->buffer_size << 1;
1396 odm_set_mac_reg(dm, R_0x7cc, BIT(30), 1);
1397 }
1398 }
1399
1400 buf->end_pos = end_pos_tmp;
1401 buf->start_pos = end_pos_tmp - buf->buffer_size;
1402 smp->smp_number_max = buf->buffer_size >> 3;
1403
1404 pr_debug("start_addr=(0x%x), end_addr=(0x%x), buffer_size=(0x%x), smp_number_max=(%d)\n",
1405 buf->start_pos, buf->end_pos, buf->buffer_size,
1406 smp->smp_number_max);
1407 }
1408
phydm_la_adc_smp_start(void * dm_void)1409 void phydm_la_adc_smp_start(void *dm_void)
1410 {
1411 struct dm_struct *dm = (struct dm_struct *)dm_void;
1412 struct rt_adcsmp *smp = &dm->adcsmp;
1413 u8 tmp_u1b = 0;
1414 u8 i = 0;
1415 u8 polling_bit = 0;
1416 u8 bkp_val = 0;
1417 boolean polling_ok = false;
1418 boolean impossible_trig_condi = (smp->en_fake_trig) ? true : false;
1419
1420 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1421 RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
1422 ("1. [BB Setting] Mode=(%d), DbgPort=(0x%x), Edge=(%d), SmpRate=(%d), Trig_Sel=(0x%x), Dma_type=(%d)\n",
1423 smp->la_trig_mode, smp->la_dbg_port, smp->la_trigger_edge,
1424 smp->la_smp_rate, smp->la_trig_sig_sel, smp->la_dma_type));
1425 #endif
1426 pr_debug("1. [BB Setting] trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x)), Dma_type = ((%d))\n",
1427 smp->la_trig_mode, smp->la_dbg_port, smp->la_trigger_edge,
1428 smp->la_smp_rate, smp->la_trig_sig_sel, smp->la_dma_type);
1429
1430 if(dm->support_ic_type & ODM_RTL8723F)
1431 bkp_val = (u8)odm_get_mac_reg(dm, R_0x1008, BIT(1));
1432
1433 phydm_la_set_mac_trigger_time(dm, smp->la_trigger_time);
1434 phydm_la_set_bb(dm);
1435 phydm_la_set_bb_dbg_port(dm, impossible_trig_condi);
1436 phydm_la_set_mac_iq_dump(dm, impossible_trig_condi);
1437
1438 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1439 watchdog_stop(dm->priv);
1440 #endif
1441
1442 if (impossible_trig_condi) {
1443 ODM_delay_ms(100);
1444 phydm_la_set_bb_dbg_port(dm, false);
1445
1446 if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) {
1447 phydm_la_set_trig_src(dm, PHYDM_ADC_MAC_TRIG);
1448 }
1449 }
1450 #if RTL8198F_SUPPORT
1451 phydm_la_pre_run(dm);
1452 #endif
1453 polling_bit = (smp->la_dump_mode == LA_BB_ADC_DUMP) ? BIT(1) : BIT(2);
1454 do { /*Polling time always use 100ms, when it exceed 2s, break loop*/
1455 if (dm->support_ic_type & ODM_RTL8192F)
1456 tmp_u1b = odm_read_1byte(dm, R_0x7f0);
1457 else
1458 tmp_u1b = odm_read_1byte(dm, R_0x7c0);
1459
1460 pr_debug("[%d] polling rpt=((0x%x))\n", i, tmp_u1b);
1461
1462 if (smp->adc_smp_state != ADCSMP_STATE_SET) {
1463 pr_debug("[state Error] state != ADCSMP_STATE_SET\n");
1464 break;
1465
1466 } else if (tmp_u1b & polling_bit) {
1467 ODM_delay_ms(100);
1468 i++;
1469 continue;
1470 } else {
1471 pr_debug("[LA Query OK] polling_bit=%d\n", polling_bit);
1472 polling_ok = true;
1473 break;
1474 }
1475 } while (i < 20);
1476
1477 if (smp->adc_smp_state == ADCSMP_STATE_SET) {
1478 if (polling_ok)
1479 phydm_la_get_tx_pkt_buf(dm);
1480 else
1481 pr_debug("[Polling timeout]\n");
1482 }
1483
1484 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
1485 watchdog_resume(dm->priv);
1486 #endif
1487
1488 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1489 if (smp->adc_smp_state == ADCSMP_STATE_SET)
1490 smp->adc_smp_state = ADCSMP_STATE_QUERY;
1491 #endif
1492
1493 pr_debug("[LA mode] la_count = ((%d))\n", smp->la_count);
1494 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1495 RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
1496 ("[LA mode] la_count = ((%d))\n", smp->la_count));
1497 #endif
1498
1499 phydm_la_stop(dm);
1500
1501 if (smp->la_count == 0) {
1502 pr_debug("LA Dump finished ---------->\n\n\n");
1503 phydm_release_bb_dbg_port(dm);
1504
1505 #if (RTL8821C_SUPPORT || RTL8195B_SUPPORT)
1506 phydm_la_clk_en(dm, false);
1507 #endif
1508 #if (RTL8723F_SUPPORT)
1509 if(dm->support_ic_type & ODM_RTL8723F)
1510 phydm_la_mac_clk_en(dm, (bkp_val == 1) ? true : false);
1511 #endif
1512 } else {
1513 smp->la_count--;
1514 pr_debug("LA Dump more ---------->\n\n\n");
1515 phydm_la_set(dm);
1516 }
1517 }
1518
phydm_la_set(void * dm_void)1519 void phydm_la_set(void *dm_void)
1520 {
1521 struct dm_struct *dm = (struct dm_struct *)dm_void;
1522 boolean is_set_success = true;
1523 struct rt_adcsmp *smp = &dm->adcsmp;
1524
1525 if (smp->adc_smp_state != ADCSMP_STATE_IDLE)
1526 is_set_success = false;
1527 else if (smp->adc_smp_buf.length == 0)
1528 is_set_success = phydm_la_buffer_allocate(dm);
1529
1530 if (!is_set_success) {
1531 pr_debug("[LA Set Fail] LA_State=(%d)\n", smp->adc_smp_state);
1532 return;
1533 }
1534
1535 smp->adc_smp_state = ADCSMP_STATE_SET;
1536
1537 pr_debug("[LA Set Success] LA_State=(%d)\n", smp->adc_smp_state);
1538
1539 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1540
1541 pr_debug("ADCSmp_work_item_index=(%d)\n", smp->la_work_item_index);
1542
1543 if (smp->la_work_item_index != 0) {
1544 odm_schedule_work_item(&smp->adc_smp_work_item_1);
1545 smp->la_work_item_index = 0;
1546 } else {
1547 odm_schedule_work_item(&smp->adc_smp_work_item);
1548 smp->la_work_item_index = 1;
1549 }
1550 #else
1551 phydm_la_adc_smp_start(dm);
1552 #endif
1553 }
1554
phydm_la_cmd(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len)1555 void phydm_la_cmd(void *dm_void, char input[][16], u32 *_used, char *output,
1556 u32 *_out_len)
1557 {
1558 struct dm_struct *dm = (struct dm_struct *)dm_void;
1559 struct rt_adcsmp *smp = &dm->adcsmp;
1560 char help[] = "-h";
1561 u32 var1[10] = {0};
1562 u32 used = *_used;
1563 u32 out_len = *_out_len;
1564
1565 if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE))
1566 return;
1567
1568 #ifdef PHYDM_COMPILE_LA_STORE_IN_IMEM
1569 if (dm->support_ic_type & PHYDM_LA_STORE_IN_IMEM_IC) {
1570 if (dm->is_download_fw)
1571 return;
1572 }
1573 #if RTL8198F_SUPPORT
1574 if (dm->support_ic_type & ODM_RTL8198F) {
1575 if (!*dm->mp_mode && !dm->priv->pmib->miscEntry.normal_LA_on) {
1576 pr_debug("plz re-set normal_LA_on = 1 & DnUp.\n");
1577 return;
1578 }
1579 }
1580 #endif
1581 #endif
1582
1583 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
1584
1585 /*@dbg_print("echo cmd input_num = %d\n", input_num);*/
1586
1587 if ((strcmp(input[1], help) == 0)) {
1588 PDM_SNPF(out_len, used, output + used, out_len - used,
1589 "=====[LA Mode Help] =============================\n");
1590 /*Trigger*/
1591 PDM_SNPF(out_len, used, output + used, out_len - used,
1592 "BB_trig: 1 0 {DbgPort Bit} {DMA#} {TrigTime} {DbgPort_head(Jgr2)}\n\t{DbgPort} {Edge: 0(P),1(N)} {f_smp:80 >> N} {Capture num}\n\n");
1593 PDM_SNPF(out_len, used, output + used, out_len - used,
1594 "MAC_trig: 1 1 {0-ok/1-fail/2-cca} {DMA#} {TrigTime} {DbgPort_head(Jgr2)}\n\t{DbgPort} {N/A} {f_smp:80 >> N} {Cpture num}\n\n");
1595 PDM_SNPF(out_len, used, output + used, out_len - used,
1596 "All: {En} {0:ADC_BB_trig,1:ADC MAC_trig,2:RF0,3:RF1,4:MAC}\n\t{BB:dbg_port[bit],BB_MAC:0-ok/1-fail/2-cca,MAC:ref} {DMA#} {TrigTime}\n\t{DbgPort_head/ref_mask} {dbg_port} {0:P_Edge, 1:N_Edge} {SpRate:0-80M,1-40M,2-20M} {Capture num}\n\n");
1597 /*Adv-Trig*/
1598 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
1599 PDM_SNPF(out_len, used, output + used, out_len - used,
1600 "adv show\n");
1601 PDM_SNPF(out_len, used, output + used, out_len - used,
1602 "adv {adv_trig_en} {0:And[0]_disable} {en}\n");
1603 PDM_SNPF(out_len, used, output + used, out_len - used,
1604 "adv {adv_trig_en} {1~3: And[3:0]} {Sel} {Val} {Inv}\n");
1605 PDM_SNPF(out_len, used, output + used, out_len - used,
1606 "adv {adv_trig_en} {4: And[4]} {BitMask} {BitVal} {Inv}\n\n");
1607 #endif
1608 /*Setting*/
1609 PDM_SNPF(out_len, used, output + used, out_len - used,
1610 "set {1:tx_buff_size} {0: half, 1:full}\n");
1611 PDM_SNPF(out_len, used, output + used, out_len - used,
1612 "set {2:Fake Trigger} {en}\n");
1613 PDM_SNPF(out_len, used, output + used, out_len - used,
1614 "set {3:Auto Print} {en}\n\n");
1615 /*Print*/
1616 PDM_SNPF(out_len, used, output + used, out_len - used,
1617 "print {0: all(Hex)}\n");
1618 PDM_SNPF(out_len, used, output + used, out_len - used,
1619 "print {1: partial} {0:hex 1:dec 2: s-dec} {bit_L} {bit_H}\n\n");
1620
1621 /*Fast Trigger*/
1622 PDM_SNPF(out_len, used, output + used, out_len - used,
1623 "fast {0: CCA trig & AGC Dbg Port}\n");
1624 PDM_SNPF(out_len, used, output + used, out_len - used,
1625 "fast {1: CCA trig & EVM Dbg Port}\n");
1626 PDM_SNPF(out_len, used, output + used, out_len - used,
1627 "fast {2: CCA trig & SNR Dbg Port}\n");
1628 PDM_SNPF(out_len, used, output + used, out_len - used,
1629 "fast {3: CCA trig & CFO Dbg Port}\n");
1630 PDM_SNPF(out_len, used, output + used, out_len - used,
1631 "fast {4: CCA trig & ADC output Dbg Port}\n");
1632 PDM_SNPF(out_len, used, output + used, out_len - used,
1633 "fast {10: EVM>=-X dB, 11: EVM<=-X dB} {X=2/4/8/16/32/64} {0:Lgcy, 1:HT}\n");
1634 PDM_SNPF(out_len, used, output + used, out_len - used,
1635 "fast {12: EVM=-X dB} {X} {0:Lgcy, 1:HT}\n");
1636 PDM_SNPF(out_len, used, output + used, out_len - used,
1637 "fast {20: RX-rate-idx=X} {X}\n");
1638
1639 PDM_SNPF(out_len, used, output + used, out_len - used,
1640 "=================================================\n");
1641 } else if ((strcmp(input[1], "print") == 0)) {
1642 phydm_la_buffer_print(dm, input, &used, output, &out_len);
1643 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
1644 } else if ((strcmp(input[1], "fast") == 0)) {
1645 phydm_la_cmd_fast_jgr3(dm, input, &used, output, &out_len);
1646
1647 } else if ((strcmp(input[1], "adv") == 0)) {
1648 phydm_la_bb_adv_cmd_jgr3(dm, input, &used, output, &out_len);
1649 #endif
1650 } else if ((strcmp(input[1], "set") == 0)) {
1651 PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
1652
1653 if (var1[1] == 1) {
1654 PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
1655 phydm_la_set_buff_mode(dm, (enum la_buff_mode)var1[2]);
1656 PDM_SNPF(out_len, used, output + used, out_len - used,
1657 "Buff_mode=(%d/2)\n", smp->la_buff_mode + 1);
1658 } else if (var1[1] == 2) {
1659 PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
1660 smp->en_fake_trig = (boolean)var1[2];
1661
1662 PDM_SNPF(out_len, used, output + used, out_len - used,
1663 "en_fake_trig=(%d)\n", smp->en_fake_trig);
1664 } else if (var1[1] == 3) {
1665 PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
1666 smp->is_la_print = (boolean)var1[2];
1667 PDM_SNPF(out_len, used, output + used, out_len - used,
1668 "Auto print=(%d)\n", smp->is_la_print);
1669 }
1670 } else if (var1[0] == 1) {
1671 PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
1672
1673 smp->la_trig_mode = (u8)var1[1];
1674
1675 if (smp->la_trig_mode == PHYDM_MAC_TRIG)
1676 PHYDM_SSCANF(input[3], DCMD_HEX, &var1[2]);
1677 else
1678 PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
1679 smp->la_trig_sig_sel = var1[2];
1680
1681 PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);
1682 PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var1[4]);
1683 PHYDM_SSCANF(input[6], DCMD_HEX, &var1[5]);
1684 PHYDM_SSCANF(input[7], DCMD_HEX, &var1[6]);
1685 PHYDM_SSCANF(input[8], DCMD_DECIMAL, &var1[7]);
1686 PHYDM_SSCANF(input[9], DCMD_DECIMAL, &var1[8]);
1687 PHYDM_SSCANF(input[10], DCMD_DECIMAL, &var1[9]);
1688
1689 smp->la_dma_type = (u8)var1[3];
1690 smp->la_trigger_time = var1[4]; /*unit: us*/
1691 smp->la_mac_mask_or_hdr_sel = var1[5];
1692 smp->la_dbg_port = var1[6];
1693 smp->la_trigger_edge = (u8)var1[7];
1694 smp->la_smp_rate = (u8)(var1[8] & 0x7);
1695 smp->la_count = var1[9];
1696
1697 pr_debug("echo lamode %d %d %d %d %d %d %x %d %d %d\n",
1698 var1[0], var1[1], var1[2], var1[3], var1[4],
1699 var1[5], var1[6], var1[7], var1[8], var1[9]);
1700 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1701 RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
1702 ("echo lamode %d %d %d %d %d %d %x %d %d %d\n",
1703 var1[0], var1[1], var1[2], var1[3],
1704 var1[4], var1[5], var1[6], var1[7],
1705 var1[8], var1[9]));
1706 #endif
1707
1708 PDM_SNPF(out_len, used, output + used, out_len - used,
1709 "a.En= ((1)), b.mode = ((%d)), c.Trig_Sel = ((0x%x)), d.Dma_type = ((%d))\n",
1710 smp->la_trig_mode, smp->la_trig_sig_sel,
1711 smp->la_dma_type);
1712 PDM_SNPF(out_len, used, output + used, out_len - used,
1713 "e.Trig_Time = ((%dus)), f.Dbg_head/mac_ref_mask = ((0x%x)), g.dbg_port = ((0x%x))\n",
1714 smp->la_trigger_time,
1715 smp->la_mac_mask_or_hdr_sel, smp->la_dbg_port);
1716 PDM_SNPF(out_len, used, output + used, out_len - used,
1717 "h.Trig_edge = ((%d)), i.smp rate = ((%d MHz)), j.Cap_num = ((%d))\n",
1718 smp->la_trigger_edge, (80 >> smp->la_smp_rate),
1719 smp->la_count);
1720
1721 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
1722 PDM_SNPF(out_len, used, output + used, out_len - used,
1723 "k.en_new_bbtrigger = ((%d))\n",
1724 smp->adv_trig_table.la_adv_bbtrigger_en);
1725 #endif
1726
1727 phydm_la_set(dm);
1728 } else {
1729 phydm_la_stop(dm);
1730 PDM_SNPF(out_len, used, output + used, out_len - used,
1731 "Disable LA mode\n");
1732 }
1733
1734 *_used = used;
1735 *_out_len = out_len;
1736 }
1737
phydm_la_stop(void * dm_void)1738 void phydm_la_stop(void *dm_void)
1739 {
1740 struct dm_struct *dm = (struct dm_struct *)dm_void;
1741 struct rt_adcsmp *smp = &dm->adcsmp;
1742
1743 smp->adc_smp_state = ADCSMP_STATE_IDLE;
1744 }
1745
phydm_la_init(void * dm_void)1746 void phydm_la_init(void *dm_void)
1747 {
1748 struct dm_struct *dm = (struct dm_struct *)dm_void;
1749 struct rt_adcsmp *smp = &dm->adcsmp;
1750 struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
1751
1752 if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE))
1753 return;
1754
1755 smp->adc_smp_state = ADCSMP_STATE_IDLE;
1756 smp->is_la_print = true;
1757 smp->en_fake_trig = false;
1758 smp->txff_page = 0xffffffff;
1759 phydm_la_set_buff_mode(dm, ADCSMP_BUFF_HALF);
1760
1761 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
1762 phydm_la_bb_adv_reset_jgr3(dm);
1763 #endif
1764 }
1765
adc_smp_de_init(void * dm_void)1766 void adc_smp_de_init(void *dm_void)
1767 {
1768 struct dm_struct *dm = (struct dm_struct *)dm_void;
1769
1770 if (!(dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE))
1771 return;
1772
1773 phydm_la_stop(dm);
1774 phydm_la_buffer_release(dm);
1775 }
1776
1777 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
adc_smp_work_item_callback(void * context)1778 void adc_smp_work_item_callback(void *context)
1779 {
1780 void *adapter = (void *)context;
1781 PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
1782 struct dm_struct *dm = &hal_data->DM_OutSrc;
1783 struct rt_adcsmp *smp = &dm->adcsmp;
1784
1785 pr_debug("[WorkItem Call back] LA_State=(%d)\n", smp->adc_smp_state);
1786 phydm_la_adc_smp_start(dm);
1787 }
1788 #endif
1789 #endif /*@endif PHYDM_LA_MODE_SUPPORT*/
1790