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Searched refs:PLLE_SS_CNTL_SSCBYP (Results 1 – 4 of 4) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra20/
H A Dclock.c624 #define PLLE_SS_CNTL_SSCBYP (1 << 12) macro
712 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
742 value &= ~PLLE_SS_CNTL_SSCBYP; in tegra_plle_enable()
/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra30/
H A Dclock.c653 #define PLLE_SS_CNTL_SSCBYP (1 << 12) macro
758 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
788 value &= ~PLLE_SS_CNTL_SSCBYP; in tegra_plle_enable()
/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra124/
H A Dclock.c938 #define PLLE_SS_CNTL_SSCBYP (1 << 12) macro
990 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET | in tegra_plle_enable()
1027 value &= ~PLLE_SS_CNTL_SSCBYP; in tegra_plle_enable()
/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra210/
H A Dclock.c1124 #define PLLE_SS_CNTL_SSCBYP (1 << 12) macro
1230 value &= ~PLLE_SS_CNTL_SSCBYP; in tegra_plle_enable()