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Searched refs:DMA0_REGISTER_OFFSET (Results 1 – 10 of 10) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/
H A Dni_dma.c62 reg = DMA_RB_RPTR + DMA0_REGISTER_OFFSET; in cayman_dma_get_rptr()
86 reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET; in cayman_dma_get_wptr()
107 reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET; in cayman_dma_set_wptr()
166 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_dma_stop()
168 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
198 reg_offset = DMA0_REGISTER_OFFSET; in cayman_dma_resume()
H A Dni.c870 case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET): in cayman_get_allowed_info_register()
1132 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); in cayman_gpu_init()
1769 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET); in cayman_gpu_check_soft_reset()
1850 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_gpu_soft_reset()
1852 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in cayman_gpu_soft_reset()
H A Dsi.c1322 case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET): in si_get_allowed_info_register()
3282 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); in si_gpu_init()
3802 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET); in si_gpu_check_soft_reset()
3884 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in si_gpu_soft_reset()
3886 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_soft_reset()
4051 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in si_gpu_pci_config_reset()
4053 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()
5539 offset = DMA0_REGISTER_OFFSET; in si_enable_dma_mgcg()
5551 offset = DMA0_REGISTER_OFFSET; in si_enable_dma_mgcg()
5958 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state()
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H A Dnid.h1301 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ macro
H A Dsid.h1812 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Dsi_dma.c32 DMA0_REGISTER_OFFSET,
598 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
600 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
603 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
605 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
657 offset = DMA0_REGISTER_OFFSET; in si_dma_set_clockgating_state()
669 offset = DMA0_REGISTER_OFFSET; in si_dma_set_clockgating_state()
H A Dsi_enums.h131 #define DMA0_REGISTER_OFFSET 0x000 macro
H A Dsid.h1875 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ macro
H A Dsi.c1009 {DMA_STATUS_REG + DMA0_REGISTER_OFFSET},
H A Dgfx_v6_0.c1716 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); in gfx_v6_0_constants_init()