Searched hist:c1aa3fa5555250dfbcae99fb6944ad24c4ee6a0b (Results 1 – 5 of 5) sorted by relevance
| /rk3399_ARM-atf/include/lib/cpus/aarch64/ |
| H A D | cortex_x3.h | c1aa3fa5555250dfbcae99fb6944ad24c4ee6a0b Thu Jan 25 21:38:46 UTC 2024 Bipin Ravi <bipin.ravi@arm.com> fix(cpus): workaround for Cortex X3 erratum 2641945
Cortex X3 erratum 2641945 is a Cat B erratum that applies to all
revisions <= r1p0 and is fixed in r1p1.
The workaround is to disable the affected L1 data cache prefetcher
by setting CPUACTLR6_EL1[41] to 1. Doing so will incur a performance
penalty of ~1%. Contact Arm for an alternate workaround that impacts
power.
SDEN documentation:
https://developer.arm.com/documentation/2055130/latest
Change-Id: Ia6d6ac8a66936c63b8aa8d7698b937f42ba8f044
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_x3.S | c1aa3fa5555250dfbcae99fb6944ad24c4ee6a0b Thu Jan 25 21:38:46 UTC 2024 Bipin Ravi <bipin.ravi@arm.com> fix(cpus): workaround for Cortex X3 erratum 2641945
Cortex X3 erratum 2641945 is a Cat B erratum that applies to all
revisions <= r1p0 and is fixed in r1p1.
The workaround is to disable the affected L1 data cache prefetcher
by setting CPUACTLR6_EL1[41] to 1. Doing so will incur a performance
penalty of ~1%. Contact Arm for an alternate workaround that impacts
power.
SDEN documentation:
https://developer.arm.com/documentation/2055130/latest
Change-Id: Ia6d6ac8a66936c63b8aa8d7698b937f42ba8f044
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
|
| /rk3399_ARM-atf/services/std_svc/errata_abi/ |
| H A D | errata_abi_main.c | c1aa3fa5555250dfbcae99fb6944ad24c4ee6a0b Thu Jan 25 21:38:46 UTC 2024 Bipin Ravi <bipin.ravi@arm.com> fix(cpus): workaround for Cortex X3 erratum 2641945
Cortex X3 erratum 2641945 is a Cat B erratum that applies to all
revisions <= r1p0 and is fixed in r1p1.
The workaround is to disable the affected L1 data cache prefetcher
by setting CPUACTLR6_EL1[41] to 1. Doing so will incur a performance
penalty of ~1%. Contact Arm for an alternate workaround that impacts
power.
SDEN documentation:
https://developer.arm.com/documentation/2055130/latest
Change-Id: Ia6d6ac8a66936c63b8aa8d7698b937f42ba8f044
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
|
| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | c1aa3fa5555250dfbcae99fb6944ad24c4ee6a0b Thu Jan 25 21:38:46 UTC 2024 Bipin Ravi <bipin.ravi@arm.com> fix(cpus): workaround for Cortex X3 erratum 2641945
Cortex X3 erratum 2641945 is a Cat B erratum that applies to all
revisions <= r1p0 and is fixed in r1p1.
The workaround is to disable the affected L1 data cache prefetcher
by setting CPUACTLR6_EL1[41] to 1. Doing so will incur a performance
penalty of ~1%. Contact Arm for an alternate workaround that impacts
power.
SDEN documentation:
https://developer.arm.com/documentation/2055130/latest
Change-Id: Ia6d6ac8a66936c63b8aa8d7698b937f42ba8f044
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | c1aa3fa5555250dfbcae99fb6944ad24c4ee6a0b Thu Jan 25 21:38:46 UTC 2024 Bipin Ravi <bipin.ravi@arm.com> fix(cpus): workaround for Cortex X3 erratum 2641945
Cortex X3 erratum 2641945 is a Cat B erratum that applies to all
revisions <= r1p0 and is fixed in r1p1.
The workaround is to disable the affected L1 data cache prefetcher
by setting CPUACTLR6_EL1[41] to 1. Doing so will incur a performance
penalty of ~1%. Contact Arm for an alternate workaround that impacts
power.
SDEN documentation:
https://developer.arm.com/documentation/2055130/latest
Change-Id: Ia6d6ac8a66936c63b8aa8d7698b937f42ba8f044
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
|