Searched hist:a0cd989dd589acaa6cddaa6617bd59dde0b8ce26 (Results 1 – 5 of 5) sorted by relevance
| /rk3399_ARM-atf/bl1/ |
| H A D | bl1.mk | a0cd989dd589acaa6cddaa6617bd59dde0b8ce26 Sun Feb 09 13:30:38 UTC 2014 Achin Gupta <achin.gupta@arm.com> Factor out translation table setup in ARM FVP port
This patch factors out the ARM FVP specific code to create MMU
translation tables so that it is possible for a boot loader stage to
create a different set of tables instead of using the default ones.
The default translation tables are created with the assumption that
the calling boot loader stage executes out of secure SRAM. This might
not be true for the BL3_2 stage in the future.
A boot loader stage can define the `fill_xlation_tables()` function as
per its requirements. It returns a reference to the level 1
translation table which is used by the common platform code to setup
the TTBR_EL3.
This patch is a temporary solution before a larger rework of
translation table creation logic is introduced.
Change-Id: I09a075d5da16822ee32a411a9dbe284718fb4ff6
|
| H A D | bl1.ld.S | a0cd989dd589acaa6cddaa6617bd59dde0b8ce26 Sun Feb 09 13:30:38 UTC 2014 Achin Gupta <achin.gupta@arm.com> Factor out translation table setup in ARM FVP port
This patch factors out the ARM FVP specific code to create MMU
translation tables so that it is possible for a boot loader stage to
create a different set of tables instead of using the default ones.
The default translation tables are created with the assumption that
the calling boot loader stage executes out of secure SRAM. This might
not be true for the BL3_2 stage in the future.
A boot loader stage can define the `fill_xlation_tables()` function as
per its requirements. It returns a reference to the level 1
translation table which is used by the common platform code to setup
the TTBR_EL3.
This patch is a temporary solution before a larger rework of
translation table creation logic is introduced.
Change-Id: I09a075d5da16822ee32a411a9dbe284718fb4ff6
|
| /rk3399_ARM-atf/bl2/ |
| H A D | bl2.ld.S | a0cd989dd589acaa6cddaa6617bd59dde0b8ce26 Sun Feb 09 13:30:38 UTC 2014 Achin Gupta <achin.gupta@arm.com> Factor out translation table setup in ARM FVP port
This patch factors out the ARM FVP specific code to create MMU
translation tables so that it is possible for a boot loader stage to
create a different set of tables instead of using the default ones.
The default translation tables are created with the assumption that
the calling boot loader stage executes out of secure SRAM. This might
not be true for the BL3_2 stage in the future.
A boot loader stage can define the `fill_xlation_tables()` function as
per its requirements. It returns a reference to the level 1
translation table which is used by the common platform code to setup
the TTBR_EL3.
This patch is a temporary solution before a larger rework of
translation table creation logic is introduced.
Change-Id: I09a075d5da16822ee32a411a9dbe284718fb4ff6
|
| /rk3399_ARM-atf/bl31/ |
| H A D | bl31.ld.S | a0cd989dd589acaa6cddaa6617bd59dde0b8ce26 Sun Feb 09 13:30:38 UTC 2014 Achin Gupta <achin.gupta@arm.com> Factor out translation table setup in ARM FVP port
This patch factors out the ARM FVP specific code to create MMU
translation tables so that it is possible for a boot loader stage to
create a different set of tables instead of using the default ones.
The default translation tables are created with the assumption that
the calling boot loader stage executes out of secure SRAM. This might
not be true for the BL3_2 stage in the future.
A boot loader stage can define the `fill_xlation_tables()` function as
per its requirements. It returns a reference to the level 1
translation table which is used by the common platform code to setup
the TTBR_EL3.
This patch is a temporary solution before a larger rework of
translation table creation logic is introduced.
Change-Id: I09a075d5da16822ee32a411a9dbe284718fb4ff6
|
| /rk3399_ARM-atf/ |
| H A D | Makefile | a0cd989dd589acaa6cddaa6617bd59dde0b8ce26 Sun Feb 09 13:30:38 UTC 2014 Achin Gupta <achin.gupta@arm.com> Factor out translation table setup in ARM FVP port
This patch factors out the ARM FVP specific code to create MMU
translation tables so that it is possible for a boot loader stage to
create a different set of tables instead of using the default ones.
The default translation tables are created with the assumption that
the calling boot loader stage executes out of secure SRAM. This might
not be true for the BL3_2 stage in the future.
A boot loader stage can define the `fill_xlation_tables()` function as
per its requirements. It returns a reference to the level 1
translation table which is used by the common platform code to setup
the TTBR_EL3.
This patch is a temporary solution before a larger rework of
translation table creation logic is introduced.
Change-Id: I09a075d5da16822ee32a411a9dbe284718fb4ff6
|