Searched hist:"9 aadf25c2251d3fe66ea743b97cf32e1728b3ae4" (Results 1 – 5 of 5) sorted by relevance
| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/ |
| H A D | suspend.h | 9aadf25c2251d3fe66ea743b97cf32e1728b3ae4 Wed May 17 08:14:37 UTC 2017 Lin Huang <hl@rock-chips.com> rockchip/rk3399: set ddr clock source back to dpll when ddr resume
when logic power rail shutdown, CRU register will back to reset
value, ddr use abpll as clock source when do suspend, we need to save
and dpll value in pmusram, then set back these ddr clock back to dpll
when dddr resume.
Change-Id: I95dc0173649e8515859cfa46b40a606e0cc2fe3f
Signed-off-by: Lin Huang <hl@rock-chips.com>
|
| H A D | suspend.c | 9aadf25c2251d3fe66ea743b97cf32e1728b3ae4 Wed May 17 08:14:37 UTC 2017 Lin Huang <hl@rock-chips.com> rockchip/rk3399: set ddr clock source back to dpll when ddr resume
when logic power rail shutdown, CRU register will back to reset
value, ddr use abpll as clock source when do suspend, we need to save
and dpll value in pmusram, then set back these ddr clock back to dpll
when dddr resume.
Change-Id: I95dc0173649e8515859cfa46b40a606e0cc2fe3f
Signed-off-by: Lin Huang <hl@rock-chips.com>
|
| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/soc/ |
| H A D | soc.c | 9aadf25c2251d3fe66ea743b97cf32e1728b3ae4 Wed May 17 08:14:37 UTC 2017 Lin Huang <hl@rock-chips.com> rockchip/rk3399: set ddr clock source back to dpll when ddr resume
when logic power rail shutdown, CRU register will back to reset
value, ddr use abpll as clock source when do suspend, we need to save
and dpll value in pmusram, then set back these ddr clock back to dpll
when dddr resume.
Change-Id: I95dc0173649e8515859cfa46b40a606e0cc2fe3f
Signed-off-by: Lin Huang <hl@rock-chips.com>
|
| H A D | soc.h | 9aadf25c2251d3fe66ea743b97cf32e1728b3ae4 Wed May 17 08:14:37 UTC 2017 Lin Huang <hl@rock-chips.com> rockchip/rk3399: set ddr clock source back to dpll when ddr resume
when logic power rail shutdown, CRU register will back to reset
value, ddr use abpll as clock source when do suspend, we need to save
and dpll value in pmusram, then set back these ddr clock back to dpll
when dddr resume.
Change-Id: I95dc0173649e8515859cfa46b40a606e0cc2fe3f
Signed-off-by: Lin Huang <hl@rock-chips.com>
|
| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/pmu/ |
| H A D | pmu.c | 9aadf25c2251d3fe66ea743b97cf32e1728b3ae4 Wed May 17 08:14:37 UTC 2017 Lin Huang <hl@rock-chips.com> rockchip/rk3399: set ddr clock source back to dpll when ddr resume
when logic power rail shutdown, CRU register will back to reset
value, ddr use abpll as clock source when do suspend, we need to save
and dpll value in pmusram, then set back these ddr clock back to dpll
when dddr resume.
Change-Id: I95dc0173649e8515859cfa46b40a606e0cc2fe3f
Signed-off-by: Lin Huang <hl@rock-chips.com>
|