Searched hist:"7428 bbf4437e046b1bd5f43506abed2fb621b7bc" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/plat/arm/board/n1sdp/ |
| H A D | n1sdp_def.h | 7428bbf4437e046b1bd5f43506abed2fb621b7bc Mon Jul 22 15:10:12 UTC 2019 Manoj Kumar <manoj.kumar3@arm.com> n1sdp: fix DMC ECC enablement sequence in N1SDP platform
The DMC-620 memory controllers in N1SDP platform has to be put
into CONFIG state before writing to ERR0CTLR0 register to enable
ECC.
This patch fixes the sequence so that DMCs are set to CONFIG
state before writing to ERR0CTLR0 register and moved back to
READY state after writing.
Change-Id: I1252f3ae0991603bb29234029cddb5fbf869c1b2
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
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| H A D | n1sdp_bl31_setup.c | 7428bbf4437e046b1bd5f43506abed2fb621b7bc Mon Jul 22 15:10:12 UTC 2019 Manoj Kumar <manoj.kumar3@arm.com> n1sdp: fix DMC ECC enablement sequence in N1SDP platform
The DMC-620 memory controllers in N1SDP platform has to be put
into CONFIG state before writing to ERR0CTLR0 register to enable
ECC.
This patch fixes the sequence so that DMCs are set to CONFIG
state before writing to ERR0CTLR0 register and moved back to
READY state after writing.
Change-Id: I1252f3ae0991603bb29234029cddb5fbf869c1b2
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
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