1de8bc83eSManoj Kumar /* 2*fe2b37f6Ssah01 * Copyright (c) 2018-2022, Arm Limited. All rights reserved. 3de8bc83eSManoj Kumar * 4de8bc83eSManoj Kumar * SPDX-License-Identifier: BSD-3-Clause 5de8bc83eSManoj Kumar */ 6de8bc83eSManoj Kumar 7de8bc83eSManoj Kumar #ifndef N1SDP_DEF_H 8de8bc83eSManoj Kumar #define N1SDP_DEF_H 9de8bc83eSManoj Kumar 10de8bc83eSManoj Kumar /* Non-secure SRAM MMU mapping */ 11de8bc83eSManoj Kumar #define N1SDP_NS_SRAM_BASE (0x06000000) 12de8bc83eSManoj Kumar #define N1SDP_NS_SRAM_SIZE (0x00010000) 13de8bc83eSManoj Kumar #define N1SDP_MAP_NS_SRAM MAP_REGION_FLAT( \ 14de8bc83eSManoj Kumar N1SDP_NS_SRAM_BASE, \ 15de8bc83eSManoj Kumar N1SDP_NS_SRAM_SIZE, \ 16de8bc83eSManoj Kumar MT_DEVICE | MT_RW | MT_SECURE) 17de8bc83eSManoj Kumar 1834c7af41SManish Pandey /* SDS Platform information defines */ 1934c7af41SManish Pandey #define N1SDP_SDS_PLATFORM_INFO_STRUCT_ID 8 2034c7af41SManish Pandey #define N1SDP_SDS_PLATFORM_INFO_OFFSET 0 2134c7af41SManish Pandey #define N1SDP_SDS_PLATFORM_INFO_SIZE 4 2234c7af41SManish Pandey #define N1SDP_MAX_DDR_CAPACITY_GB 64 23*fe2b37f6Ssah01 #define N1SDP_MAX_SECONDARY_COUNT 16 24de8bc83eSManoj Kumar 257428bbf4SManoj Kumar /* DMC memory command registers */ 267428bbf4SManoj Kumar #define N1SDP_DMC0_MEMC_CMD_REG 0x4E000008 277428bbf4SManoj Kumar #define N1SDP_DMC1_MEMC_CMD_REG 0x4E100008 287428bbf4SManoj Kumar 29de8bc83eSManoj Kumar /* DMC ERR0CTLR0 registers */ 30de8bc83eSManoj Kumar #define N1SDP_DMC0_ERR0CTLR0_REG 0x4E000708 31de8bc83eSManoj Kumar #define N1SDP_DMC1_ERR0CTLR0_REG 0x4E100708 32de8bc83eSManoj Kumar 33f91a8e4cSManish Pandey /* Remote DMC memory command registers */ 34f91a8e4cSManish Pandey #define N1SDP_REMOTE_DMC0_MEMC_CMD_REG PLAT_ARM_REMOTE_CHIP_OFFSET +\ 35f91a8e4cSManish Pandey N1SDP_DMC0_MEMC_CMD_REG 36f91a8e4cSManish Pandey #define N1SDP_REMOTE_DMC1_MEMC_CMD_REG PLAT_ARM_REMOTE_CHIP_OFFSET +\ 37f91a8e4cSManish Pandey N1SDP_DMC1_MEMC_CMD_REG 38f91a8e4cSManish Pandey 39f91a8e4cSManish Pandey /* Remote DMC ERR0CTLR0 registers */ 40f91a8e4cSManish Pandey #define N1SDP_REMOTE_DMC0_ERR0CTLR0_REG PLAT_ARM_REMOTE_CHIP_OFFSET +\ 41f91a8e4cSManish Pandey N1SDP_DMC0_ERR0CTLR0_REG 42f91a8e4cSManish Pandey #define N1SDP_REMOTE_DMC1_ERR0CTLR0_REG PLAT_ARM_REMOTE_CHIP_OFFSET +\ 43f91a8e4cSManish Pandey N1SDP_DMC1_ERR0CTLR0_REG 44f91a8e4cSManish Pandey 457428bbf4SManoj Kumar /* DMC memory commands */ 467428bbf4SManoj Kumar #define N1SDP_DMC_MEMC_CMD_CONFIG 0 477428bbf4SManoj Kumar #define N1SDP_DMC_MEMC_CMD_READY 3 487428bbf4SManoj Kumar 49de8bc83eSManoj Kumar /* DMC ECC enable bit in ERR0CTLR0 register */ 50de8bc83eSManoj Kumar #define N1SDP_DMC_ERR0CTLR0_ECC_EN 0x1 51de8bc83eSManoj Kumar 52de8bc83eSManoj Kumar #endif /* N1SDP_DEF_H */ 53