| #
420c400a |
| 16-May-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes I2fcf13b7,I153ccb43 into integration
* changes:
feat(n1sdp): add support for nt_fw_config
feat(n1sdp): enable trusted board boot on n1sdp
|
| #
cf85030e |
| 15-Mar-2022 |
sahil <sahil@arm.com> |
feat(n1sdp): add support for nt_fw_config
This patch adds support to load nt_fw_config with the information from
plat_info sds structure which is then passed from BL2 to BL33.
Signed-off-by: sahil
feat(n1sdp): add support for nt_fw_config
This patch adds support to load nt_fw_config with the information from
plat_info sds structure which is then passed from BL2 to BL33.
Signed-off-by: sahil <sahil@arm.com>
Change-Id: I2fcf13b7bf5ab042ef830157fd9cceedbdca617a
show more ...
|
| #
fe2b37f6 |
| 06-Jun-2021 |
sah01 <sahil@arm.com> |
feat(n1sdp): enable trusted board boot on n1sdp
Move from RESET_TO_BL31 boot to a TBBR style boot on N1sdp.
Signed-off-by: sahil <sahil@arm.com>
Change-Id: I153ccb43a4a013830973c7a183825d62b372c65e
|
| #
1d2b4161 |
| 31-Oct-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge changes I75799fd4,I4781dc6a into integration
* changes:
n1sdp: update platform macros for dual-chip setup
n1sdp: introduce platform information SDS region
|
| #
f91a8e4c |
| 11-Sep-2019 |
Manish Pandey <manish.pandey2@arm.com> |
n1sdp: update platform macros for dual-chip setup
N1SDP supports multichip configuration wherein n1sdp boards are
connected over high speed coherent CCIX link for now only dual-chip is
supported.
n1sdp: update platform macros for dual-chip setup
N1SDP supports multichip configuration wherein n1sdp boards are
connected over high speed coherent CCIX link for now only dual-chip is
supported.
A single instance of TF-A runs on master chip which should be aware of
slave chip's CPU and memory topology.
This patch updates platform macros to include remote chip's information
and also ensures that a single version of firmware works for both single
and dual-chip setup.
Change-Id: I75799fd46dc10527aa99585226099d836c21da70
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
show more ...
|
| #
34c7af41 |
| 07-Oct-2019 |
Manish Pandey <manish.pandey2@arm.com> |
n1sdp: introduce platform information SDS region
Platform information structure holds information about platform's DDR
size(local/remote) which will be used to zero out the memory before
enabling th
n1sdp: introduce platform information SDS region
Platform information structure holds information about platform's DDR
size(local/remote) which will be used to zero out the memory before
enabling the ECC capability as well as information about multichip
setup. Multichip and remote DDR information can only be probed in SCP,
SDS region will be used by TF-A to get this information at boot up.
This patch introduces a new SDS to store platform information, which is
populated dynamically by SCP Firmware.previously used mem_info SDS is
also made part of this structure itself.
The platform information is also passed to BL33 by copying it to Non-
Secure SRAM.
Change-Id: I4781dc6a7232c3c0a3219b164d943ce9e3e469ee
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
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|
| #
6ef6157e |
| 23-Jul-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "n1sdp: fix DMC ECC enablement sequence in N1SDP platform" into integration
|
| #
7428bbf4 |
| 22-Jul-2019 |
Manoj Kumar <manoj.kumar3@arm.com> |
n1sdp: fix DMC ECC enablement sequence in N1SDP platform
The DMC-620 memory controllers in N1SDP platform has to be put
into CONFIG state before writing to ERR0CTLR0 register to enable
ECC.
This pa
n1sdp: fix DMC ECC enablement sequence in N1SDP platform
The DMC-620 memory controllers in N1SDP platform has to be put
into CONFIG state before writing to ERR0CTLR0 register to enable
ECC.
This patch fixes the sequence so that DMCs are set to CONFIG
state before writing to ERR0CTLR0 register and moved back to
READY state after writing.
Change-Id: I1252f3ae0991603bb29234029cddb5fbf869c1b2
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
show more ...
|
| #
b4c99a9c |
| 27-Jun-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge "n1sdp: add code for DDR ECC enablement and BL33 copy to DDR" into integration
|
| #
de8bc83e |
| 21-Jun-2019 |
Manoj Kumar <manoj.kumar3@arm.com> |
n1sdp: add code for DDR ECC enablement and BL33 copy to DDR
N1SDP platform supports RDIMMs with ECC capability. To use the ECC
capability, the entire DDR memory space has to be zeroed out before
ena
n1sdp: add code for DDR ECC enablement and BL33 copy to DDR
N1SDP platform supports RDIMMs with ECC capability. To use the ECC
capability, the entire DDR memory space has to be zeroed out before
enabling the ECC bits in DMC620. Zeroing out several gigabytes of
memory from SCP is quite time consuming so functions are added that
zeros out the DDR memory from application processor which is
much faster compared to SCP. BL33 binary cannot be copied to DDR memory
before enabling ECC so this is also done by TF-A from IOFPGA-DDR3
memory to main DDR4 memory after ECC is enabled.
Original PLAT_PHY_ADDR_SPACE_SIZE was limited to 36-bits with which
the entire DDR space cannot be accessed as DRAM2 starts in base
0x8080000000. So these macros are redefined for all ARM platforms.
Change-Id: If09524fb65b421b7a368b1b9fc52c49f2ddb7846
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
show more ...
|