Searched hist:"691 bc22de951947bcc5d3bb637858fde7283781c" (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/ |
| H A D | plat_sip_calls.c | 691bc22de951947bcc5d3bb637858fde7283781c Fri Sep 23 21:28:16 UTC 2016 Varun Wadekar <vwadekar@nvidia.com> Tegra186: read activity monitor's clock counter values
This patch adds a new SMC function ID to read the refclk and coreclk
clock counter values from the Activity Monitor. The non-secure world
requires this information to calculate the CPU's frequency.
Formula: "freq = (delta_coreclk / delta_refclk) * refclk_freq"
The following CPU registers have to be set by the non-secure driver
before issuing the SMC:
X1 = MPIDR of the target core
X2 = MIDR of the target core
Change-Id: I296d835def1f5788c17640c0c456b8f8f0e90824
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| H A D | platform_t186.mk | 691bc22de951947bcc5d3bb637858fde7283781c Fri Sep 23 21:28:16 UTC 2016 Varun Wadekar <vwadekar@nvidia.com> Tegra186: read activity monitor's clock counter values
This patch adds a new SMC function ID to read the refclk and coreclk
clock counter values from the Activity Monitor. The non-secure world
requires this information to calculate the CPU's frequency.
Formula: "freq = (delta_coreclk / delta_refclk) * refclk_freq"
The following CPU registers have to be set by the non-secure driver
before issuing the SMC:
X1 = MPIDR of the target core
X2 = MIDR of the target core
Change-Id: I296d835def1f5788c17640c0c456b8f8f0e90824
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
|
| H A D | plat_setup.c | 691bc22de951947bcc5d3bb637858fde7283781c Fri Sep 23 21:28:16 UTC 2016 Varun Wadekar <vwadekar@nvidia.com> Tegra186: read activity monitor's clock counter values
This patch adds a new SMC function ID to read the refclk and coreclk
clock counter values from the Activity Monitor. The non-secure world
requires this information to calculate the CPU's frequency.
Formula: "freq = (delta_coreclk / delta_refclk) * refclk_freq"
The following CPU registers have to be set by the non-secure driver
before issuing the SMC:
X1 = MPIDR of the target core
X2 = MIDR of the target core
Change-Id: I296d835def1f5788c17640c0c456b8f8f0e90824
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
|
| /rk3399_ARM-atf/plat/nvidia/tegra/include/t186/ |
| H A D | tegra_def.h | 691bc22de951947bcc5d3bb637858fde7283781c Fri Sep 23 21:28:16 UTC 2016 Varun Wadekar <vwadekar@nvidia.com> Tegra186: read activity monitor's clock counter values
This patch adds a new SMC function ID to read the refclk and coreclk
clock counter values from the Activity Monitor. The non-secure world
requires this information to calculate the CPU's frequency.
Formula: "freq = (delta_coreclk / delta_refclk) * refclk_freq"
The following CPU registers have to be set by the non-secure driver
before issuing the SMC:
X1 = MPIDR of the target core
X2 = MIDR of the target core
Change-Id: I296d835def1f5788c17640c0c456b8f8f0e90824
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
|