Searched hist:"63 bd5b266c2d795e9100e7a2dff1fe906febeaa0" (Results 1 – 5 of 5) sorted by relevance
| /optee_os/core/arch/arm/plat-aspeed/ |
| H A D | core_pos_a32.S | 63bd5b266c2d795e9100e7a2dff1fe906febeaa0 Thu Jan 20 02:45:08 UTC 2022 Chia-Wei Wang <chiawei_wang@aspeedtech.com> arm: Add Aspeed AST2600 platform support
Aspeed AST2600 is a dual-core SoC with ARM Cortex-A7 CPU.
This patch adds the platform support for AST2600 to execute
32-bits OP-TEE on top of TrustZone features.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
|
| H A D | sub.mk | 63bd5b266c2d795e9100e7a2dff1fe906febeaa0 Thu Jan 20 02:45:08 UTC 2022 Chia-Wei Wang <chiawei_wang@aspeedtech.com> arm: Add Aspeed AST2600 platform support
Aspeed AST2600 is a dual-core SoC with ARM Cortex-A7 CPU.
This patch adds the platform support for AST2600 to execute
32-bits OP-TEE on top of TrustZone features.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
|
| H A D | conf.mk | 63bd5b266c2d795e9100e7a2dff1fe906febeaa0 Thu Jan 20 02:45:08 UTC 2022 Chia-Wei Wang <chiawei_wang@aspeedtech.com> arm: Add Aspeed AST2600 platform support
Aspeed AST2600 is a dual-core SoC with ARM Cortex-A7 CPU.
This patch adds the platform support for AST2600 to execute
32-bits OP-TEE on top of TrustZone features.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
|
| H A D | platform_config.h | 63bd5b266c2d795e9100e7a2dff1fe906febeaa0 Thu Jan 20 02:45:08 UTC 2022 Chia-Wei Wang <chiawei_wang@aspeedtech.com> arm: Add Aspeed AST2600 platform support
Aspeed AST2600 is a dual-core SoC with ARM Cortex-A7 CPU.
This patch adds the platform support for AST2600 to execute
32-bits OP-TEE on top of TrustZone features.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
|
| H A D | platform_ast2600.c | 63bd5b266c2d795e9100e7a2dff1fe906febeaa0 Thu Jan 20 02:45:08 UTC 2022 Chia-Wei Wang <chiawei_wang@aspeedtech.com> arm: Add Aspeed AST2600 platform support
Aspeed AST2600 is a dual-core SoC with ARM Cortex-A7 CPU.
This patch adds the platform support for AST2600 to execute
32-bits OP-TEE on top of TrustZone features.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
|