Searched hist:"5 f5d1ed7d5a7626b2da48f3ac423d366bbee1fd8" (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_a75.S | 5f5d1ed7d5a7626b2da48f3ac423d366bbee1fd8 Wed Feb 20 12:11:41 UTC 2019 Louis Mayencourt <louis.mayencourt@arm.com> Add workaround for errata 764081 of Cortex-A75
Implicit Error Synchronization Barrier (IESB) might not be correctly
generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all
expection levels.
Change-Id: I2a1a568668a31e4f3f38d0fba1d632ad9939e5ad
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
|
| /rk3399_ARM-atf/include/arch/aarch64/ |
| H A D | arch.h | 5f5d1ed7d5a7626b2da48f3ac423d366bbee1fd8 Wed Feb 20 12:11:41 UTC 2019 Louis Mayencourt <louis.mayencourt@arm.com> Add workaround for errata 764081 of Cortex-A75
Implicit Error Synchronization Barrier (IESB) might not be correctly
generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all
expection levels.
Change-Id: I2a1a568668a31e4f3f38d0fba1d632ad9939e5ad
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
|
| /rk3399_ARM-atf/lib/el3_runtime/aarch64/ |
| H A D | context_mgmt.c | 5f5d1ed7d5a7626b2da48f3ac423d366bbee1fd8 Wed Feb 20 12:11:41 UTC 2019 Louis Mayencourt <louis.mayencourt@arm.com> Add workaround for errata 764081 of Cortex-A75
Implicit Error Synchronization Barrier (IESB) might not be correctly
generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all
expection levels.
Change-Id: I2a1a568668a31e4f3f38d0fba1d632ad9939e5ad
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | 5f5d1ed7d5a7626b2da48f3ac423d366bbee1fd8 Wed Feb 20 12:11:41 UTC 2019 Louis Mayencourt <louis.mayencourt@arm.com> Add workaround for errata 764081 of Cortex-A75
Implicit Error Synchronization Barrier (IESB) might not be correctly
generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all
expection levels.
Change-Id: I2a1a568668a31e4f3f38d0fba1d632ad9939e5ad
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
|