Searched hist:"5 a91c439cbeb1f64b8b9830de91efad5113d3c89" (Results 1 – 7 of 7) sorted by relevance
| /rk3399_ARM-atf/plat/marvell/armada/a3k/common/aarch64/ |
| H A D | a3700_clock.S | 5a91c439cbeb1f64b8b9830de91efad5113d3c89 Fri May 14 13:52:11 UTC 2021 Pali Rohár <pali@kernel.org> fix(plat/marvell/a3720/uart): fix UART parent clock rate determination
The UART code for the A3K platform assumes that UART parent clock rate
is always 25 MHz. This is incorrect, because the xtal clock can also run
at 40 MHz (this is board specific).
The frequency of the xtal clock is determined by a value on a strapping
pin during SOC reset. The code to determine this frequency is already in
A3K's comphy driver.
Move the get_ref_clk() function from the comphy driver to a separate
file and use it for UART parent clock rate determination.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8bb18a2d020ef18fe65aa06ffa4ab205c71be92e
|
| /rk3399_ARM-atf/include/plat/marvell/armada/a3k/common/ |
| H A D | plat_marvell.h | 5a91c439cbeb1f64b8b9830de91efad5113d3c89 Fri May 14 13:52:11 UTC 2021 Pali Rohár <pali@kernel.org> fix(plat/marvell/a3720/uart): fix UART parent clock rate determination
The UART code for the A3K platform assumes that UART parent clock rate
is always 25 MHz. This is incorrect, because the xtal clock can also run
at 40 MHz (this is board specific).
The frequency of the xtal clock is determined by a value on a strapping
pin during SOC reset. The code to determine this frequency is already in
A3K's comphy driver.
Move the get_ref_clk() function from the comphy driver to a separate
file and use it for UART parent clock rate determination.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8bb18a2d020ef18fe65aa06ffa4ab205c71be92e
|
| /rk3399_ARM-atf/plat/marvell/armada/common/ |
| H A D | marvell_console.c | 5a91c439cbeb1f64b8b9830de91efad5113d3c89 Fri May 14 13:52:11 UTC 2021 Pali Rohár <pali@kernel.org> fix(plat/marvell/a3720/uart): fix UART parent clock rate determination
The UART code for the A3K platform assumes that UART parent clock rate
is always 25 MHz. This is incorrect, because the xtal clock can also run
at 40 MHz (this is board specific).
The frequency of the xtal clock is determined by a value on a strapping
pin during SOC reset. The code to determine this frequency is already in
A3K's comphy driver.
Move the get_ref_clk() function from the comphy driver to a separate
file and use it for UART parent clock rate determination.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8bb18a2d020ef18fe65aa06ffa4ab205c71be92e
|
| /rk3399_ARM-atf/plat/marvell/armada/common/aarch64/ |
| H A D | marvell_helpers.S | 5a91c439cbeb1f64b8b9830de91efad5113d3c89 Fri May 14 13:52:11 UTC 2021 Pali Rohár <pali@kernel.org> fix(plat/marvell/a3720/uart): fix UART parent clock rate determination
The UART code for the A3K platform assumes that UART parent clock rate
is always 25 MHz. This is incorrect, because the xtal clock can also run
at 40 MHz (this is board specific).
The frequency of the xtal clock is determined by a value on a strapping
pin during SOC reset. The code to determine this frequency is already in
A3K's comphy driver.
Move the get_ref_clk() function from the comphy driver to a separate
file and use it for UART parent clock rate determination.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8bb18a2d020ef18fe65aa06ffa4ab205c71be92e
|
| /rk3399_ARM-atf/plat/marvell/armada/a3k/common/include/ |
| H A D | platform_def.h | 5a91c439cbeb1f64b8b9830de91efad5113d3c89 Fri May 14 13:52:11 UTC 2021 Pali Rohár <pali@kernel.org> fix(plat/marvell/a3720/uart): fix UART parent clock rate determination
The UART code for the A3K platform assumes that UART parent clock rate
is always 25 MHz. This is incorrect, because the xtal clock can also run
at 40 MHz (this is board specific).
The frequency of the xtal clock is determined by a value on a strapping
pin during SOC reset. The code to determine this frequency is already in
A3K's comphy driver.
Move the get_ref_clk() function from the comphy driver to a separate
file and use it for UART parent clock rate determination.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8bb18a2d020ef18fe65aa06ffa4ab205c71be92e
|
| /rk3399_ARM-atf/drivers/marvell/comphy/ |
| H A D | phy-comphy-3700.c | 5a91c439cbeb1f64b8b9830de91efad5113d3c89 Fri May 14 13:52:11 UTC 2021 Pali Rohár <pali@kernel.org> fix(plat/marvell/a3720/uart): fix UART parent clock rate determination
The UART code for the A3K platform assumes that UART parent clock rate
is always 25 MHz. This is incorrect, because the xtal clock can also run
at 40 MHz (this is board specific).
The frequency of the xtal clock is determined by a value on a strapping
pin during SOC reset. The code to determine this frequency is already in
A3K's comphy driver.
Move the get_ref_clk() function from the comphy driver to a separate
file and use it for UART parent clock rate determination.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8bb18a2d020ef18fe65aa06ffa4ab205c71be92e
|
| /rk3399_ARM-atf/plat/marvell/armada/a3k/common/ |
| H A D | a3700_common.mk | 5a91c439cbeb1f64b8b9830de91efad5113d3c89 Fri May 14 13:52:11 UTC 2021 Pali Rohár <pali@kernel.org> fix(plat/marvell/a3720/uart): fix UART parent clock rate determination
The UART code for the A3K platform assumes that UART parent clock rate
is always 25 MHz. This is incorrect, because the xtal clock can also run
at 40 MHz (this is board specific).
The frequency of the xtal clock is determined by a value on a strapping
pin during SOC reset. The code to determine this frequency is already in
A3K's comphy driver.
Move the get_ref_clk() function from the comphy driver to a separate
file and use it for UART parent clock rate determination.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8bb18a2d020ef18fe65aa06ffa4ab205c71be92e
|