1*5a91c439SPali Rohár/* 2*5a91c439SPali Rohár * Copyright (C) 2018 Marvell International Ltd. 3*5a91c439SPali Rohár * 4*5a91c439SPali Rohár * SPDX-License-Identifier: BSD-3-Clause 5*5a91c439SPali Rohár * https://spdx.org/licenses 6*5a91c439SPali Rohár */ 7*5a91c439SPali Rohár 8*5a91c439SPali Rohár#include <asm_macros.S> 9*5a91c439SPali Rohár#include <platform_def.h> 10*5a91c439SPali Rohár 11*5a91c439SPali Rohár/* 12*5a91c439SPali Rohár * Below address in used only for reading, therefore no problem with concurrent 13*5a91c439SPali Rohár * Linux access. 14*5a91c439SPali Rohár */ 15*5a91c439SPali Rohár#define MVEBU_TEST_PIN_LATCH_N (MVEBU_NB_GPIO_REG_BASE + 0x8) 16*5a91c439SPali Rohár #define MVEBU_XTAL_MODE_MASK BIT(9) 17*5a91c439SPali Rohár 18*5a91c439SPali Rohár /* ----------------------------------------------------- 19*5a91c439SPali Rohár * uint32_t get_ref_clk (void); 20*5a91c439SPali Rohár * 21*5a91c439SPali Rohár * returns reference clock in MHz (25 or 40) 22*5a91c439SPali Rohár * ----------------------------------------------------- 23*5a91c439SPali Rohár */ 24*5a91c439SPali Rohár.globl get_ref_clk 25*5a91c439SPali Rohárfunc get_ref_clk 26*5a91c439SPali Rohár mov_imm x0, MVEBU_TEST_PIN_LATCH_N 27*5a91c439SPali Rohár ldr w0, [x0] 28*5a91c439SPali Rohár tst w0, #MVEBU_XTAL_MODE_MASK 29*5a91c439SPali Rohár bne 40 30*5a91c439SPali Rohár mov w0, #25 31*5a91c439SPali Rohár ret 32*5a91c439SPali Rohár40: 33*5a91c439SPali Rohár mov w0, #40 34*5a91c439SPali Rohár ret 35*5a91c439SPali Rohárendfunc get_ref_clk 36