Searched +full:uniphier +full:- +full:ld20 +full:- +full:pcie +full:- +full:phy (Results 1 – 7 of 7) sorted by relevance
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT3 // Device Tree Source for UniPhier LD20 SoC5 // Copyright (C) 2015-2016 Socionext Inc.8 #include <dt-bindings/gpio/gpio.h>9 #include <dt-bindings/gpio/uniphier-gpio.h>10 #include <dt-bindings/thermal/thermal.h>13 compatible = "socionext,uniphier-ld20";14 #address-cells = <2>;15 #size-cells = <2>;16 interrupt-parent = <&gic>;[all …]
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT5 // Derived from uniphier-ld20-global.dts.7 // Copyright (C) 2015-2017 Socionext Inc.8 // Copyright (C) 2019-2020 Linaro Ltd.10 /dts-v1/;11 #include <dt-bindings/gpio/uniphier-gpio.h>12 #include "uniphier-ld20.dtsi"16 compatible = "socionext,uniphier-ld20-akebi96",17 "socionext,uniphier-ld20";20 stdout-path = "serial0:115200n8";[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-pcie-phy.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Socionext UniPhier PCIe PHY10 This describes the devicetree bindings for PHY interface built into11 PCIe controller implemented on Socionext UniPhier SoCs.14 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>19 - socionext,uniphier-pro5-pcie-phy20 - socionext,uniphier-ld20-pcie-phy[all …]
1 # SPDX-License-Identifier: GPL-2.0-only3 # PHY drivers for Socionext platforms.7 tristate "UniPhier USB2 PHY driver"13 Enable this to support USB PHY implemented on USB2 controller14 on UniPhier SoCs. This driver provides interface to interact15 with USB 2.0 PHY that is part of the UniPhier SoC.16 In case of Pro4, it is necessary to specify this USB2 PHY instead17 of USB3 HS-PHY.20 tristate "UniPhier USB3 PHY driver"25 Enable this to support USB PHY implemented in USB3 controller[all …]
1 // SPDX-License-Identifier: GPL-2.03 * phy-uniphier-pcie.c - PHY driver for UniPhier PCIe controller15 #include <linux/phy/phy.h>21 /* PHY */68 writel(data, priv->base + PCL_PHY_TEST_I); in uniphier_pciephy_testio_write()69 readl(priv->base + PCL_PHY_TEST_O); in uniphier_pciephy_testio_write()70 readl(priv->base + PCL_PHY_TEST_O); in uniphier_pciephy_testio_write()82 val = readl(priv->base + PCL_PHY_TEST_O) & TESTO_DAT_MASK; in uniphier_pciephy_set_param()97 readl(priv->base + PCL_PHY_TEST_O); in uniphier_pciephy_set_param()104 val = readl(priv->base + PCL_PHY_RESET); in uniphier_pciephy_assert()[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later13 #include <linux/reset-controller.h>23 #define UNIPHIER_RESET_ID_END (unsigned int)(-1)59 UNIPHIER_RESETX(30, 0x2000, 19), /* SATA-PHY */67 UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (PCIe, USB3) */70 UNIPHIER_RESETX(24, 0x2008, 2), /* PCIe */81 UNIPHIER_RESETX(16, 0x2014, 4), /* USB30-PHY0 */82 UNIPHIER_RESETX(17, 0x2014, 0), /* USB30-PHY1 */83 UNIPHIER_RESETX(18, 0x2014, 2), /* USB30-PHY2 */84 UNIPHIER_RESETX(20, 0x2014, 5), /* USB31-PHY0 */[all …]
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