1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/phy/socionext,uniphier-pcie-phy.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Socionext UniPhier PCIe PHY 8*4882a593Smuzhiyun 9*4882a593Smuzhiyundescription: | 10*4882a593Smuzhiyun This describes the devicetree bindings for PHY interface built into 11*4882a593Smuzhiyun PCIe controller implemented on Socionext UniPhier SoCs. 12*4882a593Smuzhiyun 13*4882a593Smuzhiyunmaintainers: 14*4882a593Smuzhiyun - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunproperties: 17*4882a593Smuzhiyun compatible: 18*4882a593Smuzhiyun enum: 19*4882a593Smuzhiyun - socionext,uniphier-pro5-pcie-phy 20*4882a593Smuzhiyun - socionext,uniphier-ld20-pcie-phy 21*4882a593Smuzhiyun - socionext,uniphier-pxs3-pcie-phy 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun reg: 24*4882a593Smuzhiyun description: PHY register region (offset and length) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun "#phy-cells": 27*4882a593Smuzhiyun const: 0 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun clocks: 30*4882a593Smuzhiyun minItems: 1 31*4882a593Smuzhiyun maxItems: 2 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun clock-names: 34*4882a593Smuzhiyun oneOf: 35*4882a593Smuzhiyun - items: # for Pro5 36*4882a593Smuzhiyun - const: gio 37*4882a593Smuzhiyun - const: link 38*4882a593Smuzhiyun - const: link # for others 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun resets: 41*4882a593Smuzhiyun minItems: 1 42*4882a593Smuzhiyun maxItems: 2 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun reset-names: 45*4882a593Smuzhiyun oneOf: 46*4882a593Smuzhiyun - items: # for Pro5 47*4882a593Smuzhiyun - const: gio 48*4882a593Smuzhiyun - const: link 49*4882a593Smuzhiyun - const: link # for others 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun socionext,syscon: 52*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/phandle 53*4882a593Smuzhiyun description: A phandle to system control to set configurations for phy 54*4882a593Smuzhiyun 55*4882a593Smuzhiyunrequired: 56*4882a593Smuzhiyun - compatible 57*4882a593Smuzhiyun - reg 58*4882a593Smuzhiyun - "#phy-cells" 59*4882a593Smuzhiyun - clocks 60*4882a593Smuzhiyun - clock-names 61*4882a593Smuzhiyun - resets 62*4882a593Smuzhiyun - reset-names 63*4882a593Smuzhiyun 64*4882a593SmuzhiyunadditionalProperties: false 65*4882a593Smuzhiyun 66*4882a593Smuzhiyunexamples: 67*4882a593Smuzhiyun - | 68*4882a593Smuzhiyun pcie_phy: phy@66038000 { 69*4882a593Smuzhiyun compatible = "socionext,uniphier-ld20-pcie-phy"; 70*4882a593Smuzhiyun reg = <0x66038000 0x4000>; 71*4882a593Smuzhiyun #phy-cells = <0>; 72*4882a593Smuzhiyun clock-names = "link"; 73*4882a593Smuzhiyun clocks = <&sys_clk 24>; 74*4882a593Smuzhiyun reset-names = "link"; 75*4882a593Smuzhiyun resets = <&sys_rst 24>; 76*4882a593Smuzhiyun socionext,syscon = <&soc_glue>; 77*4882a593Smuzhiyun }; 78