Searched +full:tegra186 +full:- +full:emc (Results 1 – 9 of 9) sorted by relevance
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra186-clock.h>3 #include <dt-bindings/gpio/tegra186-gpio.h>4 #include <dt-bindings/interrupt-controller/arm-gic.h>5 #include <dt-bindings/mailbox/tegra186-hsp.h>6 #include <dt-bindings/memory/tegra186-mc.h>7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>8 #include <dt-bindings/power/tegra186-powergate.h>9 #include <dt-bindings/reset/tegra186-reset.h>10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>[all …]
1 // SPDX-License-Identifier: GPL-2.02 #include <dt-bindings/clock/tegra194-clock.h>3 #include <dt-bindings/gpio/tegra194-gpio.h>4 #include <dt-bindings/interrupt-controller/arm-gic.h>5 #include <dt-bindings/mailbox/tegra186-hsp.h>6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>7 #include <dt-bindings/power/tegra194-powergate.h>8 #include <dt-bindings/reset/tegra194-reset.h>9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>10 #include <dt-bindings/memory/tegra194-mc.h>[all …]
1 # SPDX-License-Identifier: GPL-2.02 tegra-mc-y := mc.o4 tegra-mc-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20.o5 tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30.o6 tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o7 tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o8 tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o9 tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o11 obj-$(CONFIG_TEGRA_MC) += tegra-mc.o13 obj-$(CONFIG_TEGRA20_EMC) += tegra20-emc.o[all …]
1 // SPDX-License-Identifier: GPL-2.0-only38 * to control the EMC frequency. The top-level directory can be found here:40 * /sys/kernel/debug/emc44 * - available_rates: This file contains a list of valid, space-separated45 * EMC frequencies.47 * - min_rate: Writing a value to this file sets the given frequency as the49 * configured EMC frequency, this will cause the frequency to be52 * - max_rate: Similarily to the min_rate file, writing a value to this file54 * the value is lower than the currently configured EMC frequency, this59 static bool tegra186_emc_validate_rate(struct tegra186_emc *emc, in tegra186_emc_validate_rate() argument[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: NVIDIA Tegra186 (and later) SoC Memory Controller10 - Jon Hunter <jonathanh@nvidia.com>11 - Thierry Reding <thierry.reding@gmail.com>14 The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split16 handles memory requests for 40-bit virtual addresses from internal clients27 pattern: "^memory-controller@[0-9a-f]+$"[all …]
2 # (C) Copyright 2010-2015 Nvidia Corporation.4 # (C) Copyright 2000-20087 # SPDX-License-Identifier: GPL-2.0+12 obj-y += spl.o13 obj-y += cpu.o15 obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o18 obj-y += ap.o19 obj-y += board.o board2.o20 obj-y += cache.o21 obj-y += clock.o[all …]
1 // SPDX-License-Identifier: GPL-2.011 #include <linux/dma-mapping.h>280 return readl(tegra->fpci_base + offset); in fpci_readl()286 writel(value, tegra->fpci_base + offset); in fpci_writel()291 return readl(tegra->ipfs_base + offset); in ipfs_readl()297 writel(value, tegra->ipfs_base + offset); in ipfs_writel()324 struct clk *clk = tegra->ss_src_clk; in tegra_xusb_set_ss_clk()338 new_parent_rate = clk_get_rate(tegra->pll_u_480m); in tegra_xusb_set_ss_clk()345 err = clk_set_parent(clk, tegra->pll_u_480m); in tegra_xusb_set_ss_clk()361 err = clk_set_parent(clk, tegra->clk_m); in tegra_xusb_set_ss_clk()[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.8 #include <linux/clk-provider.h>17 #include <dt-bindings/clock/tegra210-car.h>18 #include <dt-bindings/reset/tegra210-car.h>23 #include "clk-id.h"264 * SDM fractional divisor is 16-bit 2's complement signed number within265 * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned266 * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to275 #define sdin_get_n_eff(cfg) ((cfg)->n * PLL_SDM_COEFF + ((cfg)->sdm_data ? \[all …]
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