Searched +full:sun8i +full:- +full:h3 +full:- +full:system +full:- +full:controller (Results 1 – 14 of 14) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.0+3 ---4 $id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Allwinner A10 System Control Device Tree Bindings10 - Chen-Yu Tsai <wens@csie.org>11 - Maxime Ripard <mripard@kernel.org>14 The SRAM controller found on most Allwinner devices is represented15 by a regular node for the SRAM controller itself, with sub-nodes16 representing the SRAM handled by the SRAM controller.[all …]
1 # SPDX-License-Identifier: GPL-2.03 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: System Controller Registers R/W Device Tree Bindings10 System controller node represents a register region containing a set12 represent as any specific type of device. The typical use-case is13 for some other node's driver, or platform-specific code, to acquire20 - Lee Jones <lee.jones@linaro.org>27 - syscon30 - compatible[all …]
4 * This file is dual-licensed: you can use it either under the terms43 #include <dt-bindings/interrupt-controller/arm-gic.h>44 #include <dt-bindings/clock/sun8i-v3s-ccu.h>45 #include <dt-bindings/reset/sun8i-v3s-ccu.h>46 #include <dt-bindings/clock/sun8i-de2.h>49 #address-cells = <1>;50 #size-cells = <1>;51 interrupt-parent = <&gic>;54 #address-cells = <1>;55 #size-cells = <1>;[all …]
2 * Copyright 2017 Chen-Yu Tsai <wens@csie.org>5 * This file is dual-licensed: you can use it either under the terms44 #include <dt-bindings/interrupt-controller/arm-gic.h>45 #include <dt-bindings/clock/sun8i-de2.h>46 #include <dt-bindings/clock/sun8i-r40-ccu.h>47 #include <dt-bindings/clock/sun8i-tcon-top.h>48 #include <dt-bindings/reset/sun8i-r40-ccu.h>49 #include <dt-bindings/reset/sun8i-de2.h>50 #include <dt-bindings/thermal/thermal.h>53 #address-cells = <1>;[all …]
6 * This file is dual-licensed: you can use it either under the terms45 #include <dt-bindings/interrupt-controller/arm-gic.h>47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>48 #include <dt-bindings/clock/sun8i-de2.h>49 #include <dt-bindings/clock/sun8i-r-ccu.h>50 #include <dt-bindings/reset/sun8i-a83t-ccu.h>51 #include <dt-bindings/reset/sun8i-de2.h>52 #include <dt-bindings/reset/sun8i-r-ccu.h>53 #include <dt-bindings/thermal/thermal.h>56 interrupt-parent = <&gic>;[all …]
2 * (C) Copyright 2007-20116 * SPDX-License-Identifier: GPL-2.0+21 static int bonding_id = -1; in sunxi_get_ss_bonding_id()23 if (bonding_id != -1) in sunxi_get_ss_bonding_id()26 /* Enable Security System */ in sunxi_get_ss_bonding_id()27 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_SS); in sunxi_get_ss_bonding_id()28 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_SS); in sunxi_get_ss_bonding_id()33 /* Disable Security System again */ in sunxi_get_ss_bonding_id()34 clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_SS); in sunxi_get_ss_bonding_id()35 clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_SS); in sunxi_get_ss_bonding_id()[all …]
4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM6412 ---help---24 ---help---26 as the original A10 (mach-sun4i).30 ---help---37 ---help---38 Select this for sunxi SoCs which uses a DRAM controller like the39 DesignWare controller used in H3, mainly SoCs after H3, which do40 not have official open-source DRAM initialization code, but can41 use modified H3 DRAM initialization code.[all …]
1 # SPDX-License-Identifier: GPL-2.03 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Alexandre Torgue <alexandre.torgue@st.com>11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>12 - Jose Abreu <joabreu@synopsys.com>23 - snps,dwmac24 - snps,dwmac-3.50a25 - snps,dwmac-3.61026 - snps,dwmac-3.70a[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)3 // based on the Allwinner H3 dtsi:6 #include <dt-bindings/clock/sun50i-a64-ccu.h>7 #include <dt-bindings/clock/sun8i-de2.h>8 #include <dt-bindings/clock/sun8i-r-ccu.h>9 #include <dt-bindings/interrupt-controller/arm-gic.h>10 #include <dt-bindings/reset/sun50i-a64-ccu.h>11 #include <dt-bindings/reset/sun8i-de2.h>12 #include <dt-bindings/reset/sun8i-r-ccu.h>13 #include <dt-bindings/thermal/thermal.h>[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)4 #include <dt-bindings/interrupt-controller/arm-gic.h>5 #include <dt-bindings/clock/sun50i-h6-ccu.h>6 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>7 #include <dt-bindings/clock/sun8i-de2.h>8 #include <dt-bindings/clock/sun8i-tcon-top.h>9 #include <dt-bindings/reset/sun50i-h6-ccu.h>10 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>11 #include <dt-bindings/reset/sun8i-de2.h>12 #include <dt-bindings/thermal/thermal.h>[all …]
2 * Allwinner SoCs SRAM Controller Driver6 * Author: Maxime Ripard <maxime.ripard@free-electrons.com>62 .data = SUNXI_SRAM_DATA("A3-A4", 0x4, 0x4, 2,76 SUNXI_SRAM_MAP(1, 1, "usb-otg")),87 .compatible = "allwinner,sun4i-a10-sram-a3-a4",91 .compatible = "allwinner,sun4i-a10-sram-c1",95 .compatible = "allwinner,sun4i-a10-sram-d",99 .compatible = "allwinner,sun50i-a64-sram-c",120 seq_puts(s, "--------------------\n\n"); in sunxi_sram_show()122 for_each_child_of_node(sram_dev->of_node, sram_node) { in sunxi_sram_show()[all …]
1 // SPDX-License-Identifier: GPL-2.03 // mcp251xfd - Microchip MCP251xFD Family CAN controller driver6 // Marc Kleine-Budde <kernel@pengutronix.de>10 // CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface91 return __mcp251xfd_get_model_str(priv->devtype_data.model); in mcp251xfd_get_model_str()120 if (!priv->reg_vdd) in mcp251xfd_vdd_enable()123 return regulator_enable(priv->reg_vdd); in mcp251xfd_vdd_enable()128 if (!priv->reg_vdd) in mcp251xfd_vdd_disable()131 return regulator_disable(priv->reg_vdd); in mcp251xfd_vdd_disable()137 if (!priv->reg_xceiver) in mcp251xfd_transceiver_enable()[all …]
... -boot-2021.07/.readthedocs.yml u-boot-2021.07/Kbuild u-boot-2021.07 ...
9 -------------------------30 ``diff -u`` to make the patch easy to merge. Be prepared to get your40 See Documentation/process/coding-style.rst for guidance here.46 See Documentation/process/submitting-patches.rst for details.57 include a Signed-off-by: line. The current version of this59 Documentation/process/submitting-patches.rst.70 that the bug would present a short-term risk to other users if it76 Documentation/admin-guide/security-bugs.rst for details.81 ---------------------------------------------------95 it has been replaced by a better system and you[all …]