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Searched +full:pll1 +full:- +full:refclk (Results 1 – 13 of 13) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dnv04.c38 struct nvkm_subdev *subdev = &init->subdev; in nv04_devinit_meminit()
39 struct nvkm_device *device = subdev->device; in nv04_devinit_meminit()
115 int shift = -4; in powerctrl_1_shift()
137 shift = -4; in powerctrl_1_shift()
146 struct nvkm_device *device = init->subdev.device; in setPLL_single()
147 int chip_version = device->bios->version.chip; in setPLL_single()
150 uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1; in setPLL_single()
164 if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1)) in setPLL_single()
165 /* upclock -- write new post divider first */ in setPLL_single()
166 nvkm_wr32(device, reg, pv->log2P << 16 | (oldpll & 0xffff)); in setPLL_single()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
19 power-domains:
24 description: clock-specifier to represent input to the WIZ
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.c4 * Copyright 2007-2009 Stuart Bennett
92 if (drm->client.device.info.chipset == 0x11) { in NVSetOwner()
103 if (drm->client.device.info.chipset == 0x11) { /* set me harder */ in NVSetOwner()
132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, in nouveau_hw_decode_pll() argument
140 pllvals->log2P = (pll1 >> 16) & 0x7; in nouveau_hw_decode_pll()
141 pllvals->N2 = pllvals->M2 = 1; in nouveau_hw_decode_pll()
144 pllvals->NM1 = pll2 & 0xffff; in nouveau_hw_decode_pll()
146 if (!(pll1 & 0x1100)) in nouveau_hw_decode_pll()
147 pllvals->NM2 = pll2 >> 16; in nouveau_hw_decode_pll()
149 pllvals->NM1 = pll1 & 0xffff; in nouveau_hw_decode_pll()
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/ti/
H A Dk3-j721e-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/mux/mux.h>
9 #include <dt-bindings/mux/ti-serdes.h>
12 cmn_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
18 cmn_refclk1: clock-cmnrefclk1 {
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/OK3568_Linux_fs/u-boot/arch/arm/mach-imx/mx5/
H A Dclock.c7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/imx-regs.h>
70 ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
78 clrsetbits_le32(&mxc_ccm->cscmr1, in set_usboh3_clk()
81 clrsetbits_le32(&mxc_ccm->cscdr1, in set_usboh3_clk()
92 clrsetbits_le32(&mxc_ccm->CCGR2, in enable_usboh3_clk()
108 return -EINVAL; in enable_i2c_clk()
112 setbits_le32(&mxc_ccm->CCGR1, mask); in enable_i2c_clk()
114 clrbits_le32(&mxc_ccm->CCGR1, mask); in enable_i2c_clk()
121 clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL); in set_usb_phy_clk()
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/OK3568_Linux_fs/kernel/drivers/phy/ti/
H A Dphy-j721e-wiz.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
9 #include <dt-bindings/phy/phy.h>
11 #include <linux/clk-provider.h>
22 #include <linux/reset-controller.h>
144 .node_name = "pll0-refclk",
148 .node_name = "pll1-refclk",
152 .node_name = "refclk-dig",
163 .node_name = "pll0-refclk",
167 .node_name = "pll1-refclk",
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.c2 * Copyright © 2006-2016 Intel Corporation
32 * per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL
71 for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) { in intel_atomic_duplicate_dpll_state()
72 struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i]; in intel_atomic_duplicate_dpll_state()
74 shared_dpll[i] = pll->state; in intel_atomic_duplicate_dpll_state()
83 drm_WARN_ON(s->dev, !drm_modeset_is_locked(&s->dev->mode_config.connection_mutex)); in intel_atomic_get_shared_dpll_state()
85 if (!state->dpll_set) { in intel_atomic_get_shared_dpll_state()
86 state->dpll_set = true; in intel_atomic_get_shared_dpll_state()
88 intel_atomic_duplicate_dpll_state(to_i915(s->dev), in intel_atomic_get_shared_dpll_state()
89 state->shared_dpll); in intel_atomic_get_shared_dpll_state()
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H A Dintel_display.c2 * Copyright © 2006-2007 Intel Corporation
29 #include <linux/intel-iommu.h>
32 #include <linux/dma-resv.h>
208 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != in vlv_get_cck_clock()
222 if (dev_priv->hpll_freq == 0) in vlv_get_cck_clock_hpll()
223 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); in vlv_get_cck_clock_hpll()
225 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); in vlv_get_cck_clock_hpll()
237 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", in intel_update_czclk()
240 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", in intel_update_czclk()
241 dev_priv->czclk_freq); in intel_update_czclk()
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/OK3568_Linux_fs/kernel/drivers/phy/broadcom/
H A Dphy-brcm-sata.c1 // SPDX-License-Identifier: GPL-2.0-or-later
191 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_ctrl_base()
194 switch (priv->version) { in brcm_sata_ctrl_base()
199 dev_err(priv->dev, "invalid phy version\n"); in brcm_sata_ctrl_base()
203 return priv->ctrl_base + (port->portnum * size); in brcm_sata_ctrl_base()
209 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_phy_wr()
210 void __iomem *pcb_base = priv->phy_base; in brcm_sata_phy_wr()
213 if (priv->version == BRCM_SATA_PHY_STB_40NM) in brcm_sata_phy_wr()
214 bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE); in brcm_sata_phy_wr()
216 pcb_base += (port->portnum * SATA_PCB_REG_28NM_SPACE_SIZE); in brcm_sata_phy_wr()
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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dda850.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
24 compatible = "arm,arm926ej-s";
28 operating-points-v2 = <&opp_table>;
32 opp_table: opp-table {
33 compatible = "operating-points-v2";
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/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-npcm7xx.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk-provider.h>
20 #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
51 val = readl_relaxed(pll->pllcon); in npcm7xx_clk_pll_recalc_rate()
79 return ERR_PTR(-ENOMEM); in npcm7xx_clk_register_pll()
89 pll->pllcon = pllcon; in npcm7xx_clk_register_pll()
90 pll->hw.init = &init; in npcm7xx_clk_register_pll()
92 hw = &pll->hw; in npcm7xx_clk_register_pll()
140 * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
141 * this specific clock. Otherwise, set to -1.
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/OK3568_Linux_fs/external/rkwifibt/drivers/bcmdhd/
H A Dhndpmu.c3 * of the SiliconBackplane-based Broadcom chips.
22 * <<Broadcom-WL-IPTag/Dual:>>
341 switch (CHIPID(sih->chip)) { in BCMRAMFN()
434 if (PMUREV(sih->pmurev) >= 5) { in BCMATTACHFN()
435 pll_ctrlcnt = (sih->pmucaps & PCAP5_PC_MASK) >> PCAP5_PC_SHIFT; in BCMATTACHFN()
437 pll_ctrlcnt = (sih->pmucaps & PCAP_PC_MASK) >> PCAP_PC_SHIFT; in BCMATTACHFN()
467 if (PMUREV(sih->pmurev) >= 5) { in BCMATTACHFN()
468 vreg_ctrlcnt = (sih->pmucaps & PCAP5_VC_MASK) >> PCAP5_VC_SHIFT; in BCMATTACHFN()
470 vreg_ctrlcnt = (sih->pmucaps & PCAP_VC_MASK) >> PCAP_VC_SHIFT; in BCMATTACHFN()
497 if (PMUREV(sih->pmurev) >= 5) { in BCMATTACHFN()
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/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/
H A Dhndpmu.c3 * of the SiliconBackplane-based Broadcom chips.
22 * <<Broadcom-WL-IPTag/Dual:>>
341 switch (CHIPID(sih->chip)) { in BCMRAMFN()
434 if (PMUREV(sih->pmurev) >= 5) { in BCMATTACHFN()
435 pll_ctrlcnt = (sih->pmucaps & PCAP5_PC_MASK) >> PCAP5_PC_SHIFT; in BCMATTACHFN()
437 pll_ctrlcnt = (sih->pmucaps & PCAP_PC_MASK) >> PCAP_PC_SHIFT; in BCMATTACHFN()
467 if (PMUREV(sih->pmurev) >= 5) { in BCMATTACHFN()
468 vreg_ctrlcnt = (sih->pmucaps & PCAP5_VC_MASK) >> PCAP5_VC_SHIFT; in BCMATTACHFN()
470 vreg_ctrlcnt = (sih->pmucaps & PCAP_VC_MASK) >> PCAP_VC_SHIFT; in BCMATTACHFN()
497 if (PMUREV(sih->pmurev) >= 5) { in BCMATTACHFN()
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