Lines Matching +full:pll1 +full:- +full:refclk
3 * of the SiliconBackplane-based Broadcom chips.
22 * <<Broadcom-WL-IPTag/Dual:>>
341 switch (CHIPID(sih->chip)) { in BCMRAMFN()
434 if (PMUREV(sih->pmurev) >= 5) { in BCMATTACHFN()
435 pll_ctrlcnt = (sih->pmucaps & PCAP5_PC_MASK) >> PCAP5_PC_SHIFT; in BCMATTACHFN()
437 pll_ctrlcnt = (sih->pmucaps & PCAP_PC_MASK) >> PCAP_PC_SHIFT; in BCMATTACHFN()
467 if (PMUREV(sih->pmurev) >= 5) { in BCMATTACHFN()
468 vreg_ctrlcnt = (sih->pmucaps & PCAP5_VC_MASK) >> PCAP5_VC_SHIFT; in BCMATTACHFN()
470 vreg_ctrlcnt = (sih->pmucaps & PCAP_VC_MASK) >> PCAP_VC_SHIFT; in BCMATTACHFN()
497 if (PMUREV(sih->pmurev) >= 5) { in BCMATTACHFN()
498 cc_ctrlcnt = (sih->pmucaps & PCAP5_CC_MASK) >> PCAP5_CC_SHIFT; in BCMATTACHFN()
500 cc_ctrlcnt = (sih->pmucaps & PCAP_CC_MASK) >> PCAP_CC_SHIFT; in BCMATTACHFN()
527 ASSERT(sih->cccaps & CC_CAP_PMU); in si_pmu_set_ldo_voltage()
529 switch (CHIPID(sih->chip)) { in si_pmu_set_ldo_voltage()
573 /* rshift2 - right shift moves mask2 to bit 0, rc_shift2 - left shift in reg */ in si_pmu_set_ldo_voltage()
591 switch (CHIPID(sih->chip)) { in BCMINITFN()
598 if (CHIPREV(sih->chiprev) < 4) { in BCMINITFN()
614 pmudelay = (si_pmu_res_uptime(sih, osh, pmu, rsc->macphy_clkavail, FALSE) + in BCMINITFN()
615 D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp - 1) / ilp); in BCMINITFN()
624 pmudelay = si_pmu_res_uptime(sih, osh, pmu, rsc->ht_avail, FALSE) + in BCMINITFN()
655 ASSERT(sih->cccaps & CC_CAP_PMU); in BCMINITFN()
666 * 43602 is the only non-AOB chip supported now in BCMINITFN()
675 pmu_fast_trans_en = (R_REG(osh, &pmu->pmucontrol_ext) & PCTL_EXT_FAST_TRANS_ENAB) ? in BCMINITFN()
680 switch (CHIPID(sih->chip)) { in BCMINITFN()
687 rsc->macphy_clkavail, pmu_fast_trans_en); in BCMINITFN()
690 rsc->macphy_aux_clkavail, pmu_fast_trans_en); in BCMINITFN()
701 rsc->macphy_clkavail, pmu_fast_trans_en); in BCMINITFN()
704 rsc->macphy_aux_clkavail, pmu_fast_trans_en); in BCMINITFN()
707 rsc->macphy_scan_clkavail, pmu_fast_trans_en); in BCMINITFN()
740 pmu_fast_trans_en = (R_REG(osh, &pmu->pmucontrol_ext) & PCTL_EXT_FAST_TRANS_ENAB) ? in BCMINITFN()
762 delay = si_pmu_fast_pwrup_delay_rsrc(sih, osh, rsc->dig_ready); in BCMINITFN()
799 #define RES_DEPEND_REMOVE -1 /* Remove from the dependencies mask */
849 /* JIRA HW43602-131 : PCIe SERDES dependency problem */
975 /* Need to change elements here, should get default values for this - 4360B1 */
1710 if ((CHIPID(sih->chip) == BCM4360_CHIP_ID || CHIPID(sih->chip) == BCM43460_CHIP_ID) && in si_pmu_avbtimer_enable()
1711 CHIPREV(sih->chiprev) >= 0x3) { in si_pmu_avbtimer_enable()
1712 int cst_ht = CST4360_RSRC_INIT_MODE(sih->chipst) & 0x1; in si_pmu_avbtimer_enable()
1715 min_mask = R_REG(osh, &pmu->min_res_mask); in si_pmu_avbtimer_enable()
1716 max_mask = R_REG(osh, &pmu->max_res_mask); in si_pmu_avbtimer_enable()
1722 W_REG(osh, &pmu->min_res_mask, min_mask); in si_pmu_avbtimer_enable()
1723 W_REG(osh, &pmu->max_res_mask, max_mask); in si_pmu_avbtimer_enable()
1725 AND_REG(osh, &pmu->min_res_mask, in si_pmu_avbtimer_enable()
1727 AND_REG(osh, &pmu->min_res_mask, in si_pmu_avbtimer_enable()
1729 AND_REG(osh, &pmu->max_res_mask, in si_pmu_avbtimer_enable()
1731 AND_REG(osh, &pmu->max_res_mask, in si_pmu_avbtimer_enable()
1753 switch (CHIPID(sih->chip)) { in si_pmu_res_masks()
1756 if (CHIPREV(sih->chiprev) >= 0x4) { in si_pmu_res_masks()
1759 /* Continue - Don't break */ in si_pmu_res_masks()
1762 if (CHIPREV(sih->chiprev) >= 0x3) { in si_pmu_res_masks()
1764 int cst_ht = CST4360_RSRC_INIT_MODE(sih->chipst) & 0x1; in si_pmu_res_masks()
1783 if (sih->chippkg == BCM43602_12x12_PKG_ID) /* LPLDO WAR */ in si_pmu_res_masks()
1793 ASSERT(sih->chippkg != BCM43602_12x12_PKG_ID); in si_pmu_res_masks()
1873 * PMU register - min_res_mask and remove the code in SR_ENAB() portion in si_pmu_res_masks()
1943 rsrcs = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT; in si_pmu_resdeptbl_upd()
1945 while (tablesz--) { in si_pmu_resdeptbl_upd()
1953 W_REG(osh, &pmu->res_table_sel, i); in si_pmu_resdeptbl_upd()
1958 W_REG(osh, &pmu->res_dep_mask, in si_pmu_resdeptbl_upd()
1964 OR_REG(osh, &pmu->res_dep_mask, in si_pmu_resdeptbl_upd()
1970 AND_REG(osh, &pmu->res_dep_mask, in si_pmu_resdeptbl_upd()
1991 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
2075 ASSERT(sih->cccaps & CC_CAP_PMU); in BCMATTACHFN()
2090 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
2093 if (CHIPREV(sih->chiprev) < 4) { in BCMATTACHFN()
2110 if (sih->chippkg == BCM43602_12x12_PKG_ID) { /* LPLDO WAR */ in BCMATTACHFN()
2131 if (CHIPREV(sih->chiprev) == 0) { in BCMATTACHFN()
2144 if (CHIPREV(sih->chiprev) == 0) { in BCMATTACHFN()
2211 if (PMUREV(sih->pmurev) == 39) { in BCMATTACHFN()
2237 if (PMUREV(sih->pmurev) == 39) { in BCMATTACHFN()
2338 while (pmu_res_updown_table_sz--) { in BCMATTACHFN()
2343 W_REG(osh, &pmu->res_table_sel, in BCMATTACHFN()
2345 W_REG(osh, &pmu->res_updn_timer, in BCMATTACHFN()
2351 rsrcs = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT; in BCMATTACHFN()
2362 if (PMUREV(sih->pmurev) >= 13) { in BCMATTACHFN()
2370 W_REG(osh, &pmu->res_table_sel, (uint32)i); in BCMATTACHFN()
2371 W_REG(osh, &pmu->res_updn_timer, r_val); in BCMATTACHFN()
2376 while (pmu_res_subst_trans_tmr_table_sz --) { in BCMATTACHFN()
2382 W_REG(osh, &pmu->res_table_sel, in BCMATTACHFN()
2386 W_REG(osh, &pmu->rsrc_substate_trans_tmr, in BCMATTACHFN()
2400 W_REG(osh, &pmu->res_table_sel, (uint32)i); in BCMATTACHFN()
2401 W_REG(osh, &pmu->res_dep_mask, (uint32)bcm_strtoul(val, NULL, 0)); in BCMATTACHFN()
2413 if (BUSTYPE(sih->bustype) == PCI_BUS || BUSTYPE(sih->bustype) == SI_BUS) { in BCMATTACHFN()
2414 bool is_pciedev = BCM43602_CHIP(sih->chip); in BCMATTACHFN()
2448 if (((CHIPID(sih->chip) == BCM4360_CHIP_ID) || (CHIPID(sih->chip) == BCM4352_CHIP_ID)) && in BCMATTACHFN()
2449 (CHIPREV(sih->chiprev) < 4) && in BCMATTACHFN()
2450 ((CST4360_RSRC_INIT_MODE(sih->chipst) & 1) == 0)) { in BCMATTACHFN()
2456 } else if (((CHIPID(sih->chip) == BCM4360_CHIP_ID) || in BCMATTACHFN()
2457 (CHIPID(sih->chip) == BCM4352_CHIP_ID)) && in BCMATTACHFN()
2458 (CHIPREV(sih->chiprev) >= 4) && in BCMATTACHFN()
2459 ((CST4360_RSRC_INIT_MODE(sih->chipst) & 1) == 0)) { in BCMATTACHFN()
2462 /* Enable REFCLK bit 11 */ in BCMATTACHFN()
2486 OR_REG(osh, &pmu->max_res_mask, max_mask); in BCMATTACHFN()
2495 OR_REG(osh, &pmu->max_res_mask, min_mask); in BCMATTACHFN()
2501 W_REG(osh, &pmu->min_res_mask, min_mask); in BCMATTACHFN()
2507 W_REG(osh, &pmu->max_res_mask, max_mask); in BCMATTACHFN()
2519 if (((CHIPID(sih->chip) == BCM4360_CHIP_ID) || (CHIPID(sih->chip) == BCM4352_CHIP_ID)) && in BCMATTACHFN()
2520 (BUSTYPE(sih->bustype) == PCI_BUS) && in BCMATTACHFN()
2521 (CHIPREV(sih->chiprev) < 4)) { in BCMATTACHFN()
2538 uint16 fref; /* x-tal frequency in [hz] */
2539 uint8 xf; /* x-tal index as contained in PMU control reg, see PMU programmers guide */
2662 * given an x-tal frequency, this table specifies the PLL params to use to generate a 960Mhz output
2770 * The table with the values of the registers will have one - one mapping.
2773 uint16 clock; /**< x-tal frequency in [KHz] */
2822 * Even though macro suggests XTALTAB0_960_37400K --> BBPLL VCO is set to 963MHz
2835 * freq table : pll1 : fvco 960.1M, pll2 for arm : 400 MHz
2839 /* Default values for unused registers 4-7 as sw loop execution will go for 8 times */
2854 * Even though macro suggests XTALTAB0_960_37400K --> BBPLL VCO is set to 963MHz
2862 * freq table : pll1 : fvco 960.1M, pll2 for arm : 400 MHz
2868 /* Default values for unused registers 4-7 as sw loop execution will go for 8 times */
2902 switch (CHIPID(sih->chip)) { in BCMPOSTTRAPFN()
2925 PMU_MSG(("si_pmu1_xtaltab0: Unknown chipid %s\n", bcm_chipname(sih->chip, chn, 8))); in BCMPOSTTRAPFN()
2940 switch (CHIPID(sih->chip)) { in BCMPOSTTRAPFN()
2969 PMU_MSG(("si_pmu1_xtaldef0: Unknown chipid %s\n", bcm_chipname(sih->chip, chn, 8))); in BCMPOSTTRAPFN()
3013 rounding_const = 1 << (BBPLL_NDIV_FRAC_BITS - 1); in BCMPOSTTRAPFN()
3028 rounding_const = 1 << (P1_DIV_SCALE_BITS - 1); in BCMPOSTTRAPFN()
3089 rounding_const = 1 << (PMU43012_PLL_NDIV_FRAC_BITS - 1); in BCMPOSTTRAPFN()
3094 rounding_const = 1 << (PMU43012_PLL_P_DIV_SCALE_BITS - 1); in BCMPOSTTRAPFN()
3114 switch (CHIPID(sih->chip)) { in BCMPOSTTRAPFN()
3150 PMU_MSG(("si_pmu1_pllfvco0: Unknown chipid %s\n", bcm_chipname(sih->chip, chn, 8))); in BCMPOSTTRAPFN()
3167 switch (CHIPID(sih->chip)) { in BCMPOSTTRAPFN()
3174 return SI_INFO(sih)->armpllclkfreq ? si_get_armpllclkfreq(sih) * 1000 : FVCO_1002p8; in BCMPOSTTRAPFN()
3182 bcm_chipname(sih->chip, chn, 8))); in BCMPOSTTRAPFN()
3200 xf = (R_REG(osh, &pmu->pmucontrol) & PCTL_XTALFREQ_MASK) >> in BCMPOSTTRAPFN()
3202 for (xt = si_pmu1_xtaltab0(sih); xt != NULL && xt->fref != 0; xt ++) in BCMPOSTTRAPFN()
3203 if (xt->xf == xf) in BCMPOSTTRAPFN()
3206 if (xt == NULL || xt->fref == 0) in BCMPOSTTRAPFN()
3208 ASSERT(xt != NULL && xt->fref != 0); in BCMPOSTTRAPFN()
3210 switch (CHIPID(sih->chip)) in BCMPOSTTRAPFN()
3226 return (xt->fref * 1000) / xtdiv; in BCMPOSTTRAPFN()
3240 uint32 ht_req = (PMURES_BIT(rsc->ht_avail) | PMURES_BIT(rsc->macphy_clkavail)); in si_pmu_htclk_mask()
3242 switch (CHIPID(sih->chip)) in si_pmu_htclk_mask()
3257 ht_req |= PMURES_BIT(rsc->ht_start); in si_pmu_htclk_mask()
3275 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
3303 * The BBPLL register set needs to be reprogrammed because the x-tal frequency is not known at
3309 * x-tal frequency and spur mode
3325 if (PMUREV(sih->pmurev) >= 5) { in si_pmu_pllctrlreg_update()
3326 pll_ctrlcnt = (sih->pmucaps & PCAP5_PC_MASK) >> PCAP5_PC_SHIFT; in si_pmu_pllctrlreg_update()
3328 pll_ctrlcnt = (sih->pmucaps & PCAP_PC_MASK) >> PCAP_PC_SHIFT; in si_pmu_pllctrlreg_update()
3347 /* for 4369, arm clk cycle can be set from nvram - default is 400 MHz */ in si_pmu_pllctrlreg_update()
3348 if ((BCM4369_CHIP(sih->chip) || BCM4362_CHIP(sih->chip)) && in si_pmu_pllctrlreg_update()
3376 /* ndiv_frac = (uint32) (((uint64) (fvco * p1div - xtal * ndiv_int) * (1 << 20)) / xtal) */ in si_pmu_pll28nm_calc_ndiv()
3377 math_uint64_multiple_add(&temp_high, &temp_low, fvco * p1div - xtal * (*ndiv_int), 1 << 20, in si_pmu_pll28nm_calc_ndiv()
3386 switch (CHIPID(sih->chip)) { in si_pmu_armpll_freq_upd()
3429 switch (CHIPID(sih->chip)) { in si_pmu_bbpll_freq_upd()
3449 switch (CHIPID(sih->chip)) { in si_pmu_armpll_chmdiv_upd()
3463 switch (CHIPID(sih->chip)) { in si_pmu_armpll_write_required()
3488 * Chip-specific overrides to PLLCONTROL registers during init. If certain conditions (dependent on
3489 * x-tal frequency and current ALP frequency) are met, an update of the PLL is required.
3510 /* points at a set of PLL register values to write for a given x-tal frequency: */ in BCMATTACHFN()
3546 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
3592 * 43602 has only 1 x-tal value, possibly insert case when an other BBPLL in BCMATTACHFN()
3623 tmp = R_REG(osh, &pmu->pmucontrol) & in BCMATTACHFN()
3625 tmp |= (((((xtal + 127) / 128) - 1) << PCTL_ILP_DIV_SHIFT) & in BCMATTACHFN()
3628 W_REG(osh, &pmu->pmucontrol, tmp); in BCMATTACHFN()
3651 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
3697 for (xt = si_pmu1_xtaltab0(sih); xt != NULL && xt->fref != 0; xt ++) in BCMATTACHFN()
3698 if (xt->fref == xtal) { in BCMATTACHFN()
3706 if (xt == NULL || xt->fref == 0) { in BCMATTACHFN()
3711 if (((R_REG(osh, &pmu->pmucontrol) & in BCMATTACHFN()
3712 PCTL_XTALFREQ_MASK) >> PCTL_XTALFREQ_SHIFT) == xt->xf) { in BCMATTACHFN()
3716 PMU_MSG(("XTAL %d.%d MHz (%d)\n", xtal / 1000, xtal % 1000, xt->xf)); in BCMATTACHFN()
3717 PMU_MSG(("Programming PLL for %d.%d MHz\n", xt->fref / 1000, xt->fref % 1000)); in BCMATTACHFN()
3719 if (BCM4389_CHIP(sih->chip)) { in BCMATTACHFN()
3721 tmp = ((xt->ndiv_int << PMU4389_ARMPLL_I_NDIV_INT_SHIFT) in BCMATTACHFN()
3725 } else if (BCM4388_CHIP(sih->chip)) { in BCMATTACHFN()
3727 tmp = ((xt->ndiv_int << PMU4388_ARMPLL_I_NDIV_INT_SHIFT) in BCMATTACHFN()
3731 } else if (BCM4369_CHIP(sih->chip) || in BCMATTACHFN()
3732 BCM4362_CHIP(sih->chip) || in BCMATTACHFN()
3737 tmp = ((xt->p1div << PMU4369_PLL0_PC2_PDIV_SHIFT) & in BCMATTACHFN()
3743 tmp = ((xt->ndiv_int << PMU4369_PLL0_PC2_NDIV_INT_SHIFT) in BCMATTACHFN()
3749 tmp = ((xt->ndiv_frac << PMU4369_PLL0_PC3_NDIV_FRAC_SHIFT) & in BCMATTACHFN()
3755 tmp = ((xt->p1div << PMU1_PLL0_PC0_P1DIV_SHIFT) & in BCMATTACHFN()
3757 ((xt->p2div << PMU1_PLL0_PC0_P2DIV_SHIFT) & in BCMATTACHFN()
3763 tmp = ((xt->ndiv_int << PMU1_PLL0_PC2_NDIV_INT_SHIFT) in BCMATTACHFN()
3770 tmp = ((xt->ndiv_frac << PMU1_PLL0_PC3_NDIV_FRAC_SHIFT) & in BCMATTACHFN()
3777 tmp = R_REG(osh, &pmu->pmucontrol) & in BCMATTACHFN()
3779 tmp |= (((((xt->fref + 127) / 128) - 1) << PCTL_ILP_DIV_SHIFT) & in BCMATTACHFN()
3781 ((xt->xf << PCTL_XTALFREQ_SHIFT) & PCTL_XTALFREQ_MASK); in BCMATTACHFN()
3782 W_REG(osh, &pmu->pmucontrol, tmp); in BCMATTACHFN()
3812 start = R_REG(osh, &pmu->pmutimer); in BCMPOSTTRAPFN()
3813 if (start != R_REG(osh, &pmu->pmutimer)) in BCMPOSTTRAPFN()
3814 start = R_REG(osh, &pmu->pmutimer); in BCMPOSTTRAPFN()
3855 (pmutime_val - prev_val) : in BCMPOSTTRAPFN()
3881 res_pend = R_REG(osh, &pmu->res_pending); in BCMPOSTTRAPFN()
3929 sii->res_pend_count = 0; in BCMPOSTTRAPFN()
3938 sii->res_state[sii->res_pend_count].low_time = in BCMPOSTTRAPFN()
3940 sii->res_state[sii->res_pend_count].low = R_REG(osh, &pmu->res_pending); in BCMPOSTTRAPFN()
3948 /* wait to check if any resource comes back to non-zero indicating in BCMPOSTTRAPFN()
3954 pmutime_prev = R_REG(osh, &pmu->pmutimer); in BCMPOSTTRAPFN()
3960 sii->res_state[sii->res_pend_count].high_time = in BCMPOSTTRAPFN()
3962 sii->res_state[sii->res_pend_count].high = R_REG(osh, &pmu->res_pending); in BCMPOSTTRAPFN()
3982 sii->res_pend_count++; in BCMPOSTTRAPFN()
3983 sii->res_pend_count %= RES_PEND_STATS_COUNT; in BCMPOSTTRAPFN()
3984 pmutime_prev = R_REG(osh, &pmu->pmutimer); in BCMPOSTTRAPFN()
4010 delay = ((current - initial) * 1000) / si_xtalfreq(sih); in si_pmu_pll_delay_43012()
4044 rsrc_ht = R_REG(osh, &pmu->res_state) & in si_pmu_pll_on_43012()
4049 /* Wait for PLL to lock in close-loop */ in si_pmu_pll_on_43012()
4053 /* Wait for 1 us for the open-loop clock to start */ in si_pmu_pll_on_43012()
4093 /** Turn Off the PLL - Required before setting the PLL registers */
4101 *min_mask = R_REG(osh, &pmu->min_res_mask); in si_pmu_pll_off()
4102 *max_mask = R_REG(osh, &pmu->max_res_mask); in si_pmu_pll_off()
4109 if ((CHIPID(sih->chip) == BCM43012_CHIP_ID) || in si_pmu_pll_off()
4110 (CHIPID(sih->chip) == BCM43013_CHIP_ID) || in si_pmu_pll_off()
4111 (CHIPID(sih->chip) == BCM43014_CHIP_ID) || in si_pmu_pll_off()
4112 (BCM4369_CHIP(sih->chip)) || in si_pmu_pll_off()
4113 (BCM4362_CHIP(sih->chip)) || in si_pmu_pll_off()
4114 (BCM4376_CHIP(sih->chip)) || in si_pmu_pll_off()
4115 (BCM4378_CHIP(sih->chip)) || in si_pmu_pll_off()
4116 (BCM4385_CHIP(sih->chip)) || in si_pmu_pll_off()
4117 (BCM4387_CHIP(sih->chip)) || in si_pmu_pll_off()
4118 (BCM4388_CHIP(sih->chip)) || in si_pmu_pll_off()
4119 (BCM4389_CHIP(sih->chip)) || in si_pmu_pll_off()
4120 BCM43602_CHIP(sih->chip) || in si_pmu_pll_off()
4129 OR_REG(osh, &pmu->max_res_mask, ht_req); in si_pmu_pll_off()
4137 if ((CHIPID(sih->chip) == BCM43012_CHIP_ID) || in si_pmu_pll_off()
4138 (CHIPID(sih->chip) == BCM43013_CHIP_ID) || in si_pmu_pll_off()
4139 (CHIPID(sih->chip) == BCM43014_CHIP_ID)) { in si_pmu_pll_off()
4142 AND_REG(osh, &pmu->min_res_mask, ~ht_req); in si_pmu_pll_off()
4143 AND_REG(osh, &pmu->max_res_mask, ~ht_req); in si_pmu_pll_off()
4154 /** Turn Off the PLL - Required before setting the PLL registers */
4175 *min_mask = R_REG(osh, &pmu->min_res_mask); in si_pmu_pll_off_PARR()
4176 *max_mask = R_REG(osh, &pmu->max_res_mask); in si_pmu_pll_off_PARR()
4186 if ((CHIPID(sih->chip) == BCM43012_CHIP_ID) || in si_pmu_pll_off_PARR()
4187 (CHIPID(sih->chip) == BCM43013_CHIP_ID) || in si_pmu_pll_off_PARR()
4188 (CHIPID(sih->chip) == BCM43014_CHIP_ID) || in si_pmu_pll_off_PARR()
4189 (BCM4369_CHIP(sih->chip)) || in si_pmu_pll_off_PARR()
4190 (BCM4362_CHIP(sih->chip)) || in si_pmu_pll_off_PARR()
4191 (BCM4376_CHIP(sih->chip)) || in si_pmu_pll_off_PARR()
4192 (BCM4378_CHIP(sih->chip)) || in si_pmu_pll_off_PARR()
4193 (BCM4385_CHIP(sih->chip)) || in si_pmu_pll_off_PARR()
4194 (BCM4387_CHIP(sih->chip)) || in si_pmu_pll_off_PARR()
4195 (BCM4388_CHIP(sih->chip)) || in si_pmu_pll_off_PARR()
4196 (BCM4389_CHIP(sih->chip)) || in si_pmu_pll_off_PARR()
4197 (BCM4397_CHIP(sih->chip)) || in si_pmu_pll_off_PARR()
4198 (BCM43602_CHIP(sih->chip)) || in si_pmu_pll_off_PARR()
4208 OR_REG(osh, &pmu->max_res_mask, ht_req); in si_pmu_pll_off_PARR()
4216 AND_REG(osh, &pmu->min_res_mask, ~ht_req); in si_pmu_pll_off_PARR()
4217 AND_REG(osh, &pmu->max_res_mask, ~ht_req); in si_pmu_pll_off_PARR()
4239 OR_REG(osh, &pmu->max_res_mask, max_mask_mask); in si_pmu_pll_on()
4242 OR_REG(osh, &pmu->min_res_mask, min_mask_mask); in si_pmu_pll_on()
4252 if ((CHIPID(sih->chip) == BCM43012_CHIP_ID) || in si_pmu_pll_on()
4253 (CHIPID(sih->chip) == BCM43013_CHIP_ID) || in si_pmu_pll_on()
4254 (CHIPID(sih->chip) == BCM43014_CHIP_ID)) { in si_pmu_pll_on()
4277 if (PMUREV(sih->pmurev) >= 5) { in BCMATTACHFN()
4278 pll_ctrlcnt = (sih->pmucaps & PCAP5_PC_MASK) >> PCAP5_PC_SHIFT; in BCMATTACHFN()
4280 pll_ctrlcnt = (sih->pmucaps & PCAP_PC_MASK) >> PCAP_PC_SHIFT; in BCMATTACHFN()
4297 /* If no OTP parameter is found and no chip-specific updates are needed, return. */ in BCMATTACHFN()
4305 if ((BCM4369_CHIP(sih->chip) || BCM4362_CHIP(sih->chip)) && in BCMATTACHFN()
4335 /* for 4369, arm clk cycle can be set from nvram - default is 400 MHz */ in BCMATTACHFN()
4336 if ((BCM4369_CHIP(sih->chip) || BCM4362_CHIP(sih->chip)) && in BCMATTACHFN()
4344 if (PMUREV(sih->pmurev) >= 2) in BCMATTACHFN()
4345 OR_REG(osh, &pmu->pmucontrol, PCTL_PLL_PLLCTL_UPD); in BCMATTACHFN()
4369 /* Update any chip-specific PLL registers. Does not write PLL 'update' bit yet. */ in BCMATTACHFN()
4376 if (PMUREV(sih->pmurev) >= 2) in BCMATTACHFN()
4377 OR_REG(osh, &pmu->pmucontrol, PCTL_PLL_PLLCTL_UPD); in BCMATTACHFN()
4384 if ((CHIPID(sih->chip) == BCM43012_CHIP_ID) || in BCMATTACHFN()
4385 (CHIPID(sih->chip) == BCM43013_CHIP_ID) || in BCMATTACHFN()
4386 (CHIPID(sih->chip) == BCM43014_CHIP_ID)) { in BCMATTACHFN()
4391 W_REG(osh, &pmu->clkstretch, CSTRETCH_REDUCE_8); in BCMATTACHFN()
4423 switch (CHIPID(sih->chip)) { in si_pmu_get_backplaneclkspeed()
4436 switch (CHIPID(sih->chip)) { in si_pmu_get_backplaneclkspeed()
4476 if (PMUREV(sih->pmurev) >= 2) in si_pmu_update_backplane_clock()
4477 OR_REG(osh, &pmu->pmucontrol, PCTL_PLL_PLLCTL_UPD); in si_pmu_update_backplane_clock()
4526 if (BCM43602_CHIP(sih->chip) && in BCMPOSTTRAPFN()
4537 switch (CHIPID(sih->chip)) { in BCMPOSTTRAPFN()
4579 PMU_MSG(("si_pmu1_cpuclk0: Unknown chipid %s\n", bcm_chipname(sih->chip, chn, 8))); in BCMPOSTTRAPFN()
4597 if (BCM4362_CHIP(sih->chip) || in BCMPOSTTRAPFN()
4598 BCM4369_CHIP(sih->chip)) { in BCMPOSTTRAPFN()
4603 } else if (BCM4378_CHIP(sih->chip) || BCM4376_CHIP(sih->chip)) { in BCMPOSTTRAPFN()
4618 if (BCM4369_CHIP(sih->chip) || BCM4362_CHIP(sih->chip) || in BCMPOSTTRAPFN()
4619 BCM4376_CHIP(sih->chip) || in BCMPOSTTRAPFN()
4620 BCM4378_CHIP(sih->chip) || in BCMPOSTTRAPFN()
4698 switch (CHIPID(sih->chip)) { in si_mac_clk()
4707 bcm_chipname(CHIPID(sih->chip), chn, 8))); in si_mac_clk()
4718 /* 4387 pll MAC channel divisor - for ftm */
4754 switch (CHIPID(sih->chip)) { in si_pmu_fvco_macdiv()
4798 PMU_MSG(("si_mac_clk: Unknown chipid %s\n", bcm_chipname(sih->chip, chn, 8))); in si_pmu_fvco_macdiv()
4826 ret_ctl = R_REG(osh, &pmu->retention_ctl); in BCMPOSTTRAPFN()
4828 W_REG(osh, &pmu->retention_ctl, ret_ctl); in BCMPOSTTRAPFN()
4838 /** Return TRUE if pmu rsrc XTAL_PU was de-asserted */
4855 if (PMUREV(sih->pmurev) >= 36) { in BCMPOSTTRAPFN()
4856 uint32 pmu_int_sts = R_REG(osh, &pmu->pmuintstatus); in BCMPOSTTRAPFN()
4859 W_REG(osh, &pmu->pmuintstatus, PMU_INT_STAT_RSRC_EVENT_INT0_MASK); in BCMPOSTTRAPFN()
4889 switch (CHIPID(sih->chip)) { in si_pmu_switch_on_PARLDO()
4891 mask = R_REG(osh, &pmu->min_res_mask) | PMURES_BIT(RES43602_PARLDO_PU); in si_pmu_switch_on_PARLDO()
4892 W_REG(osh, &pmu->min_res_mask, mask); in si_pmu_switch_on_PARLDO()
4893 mask = R_REG(osh, &pmu->max_res_mask) | PMURES_BIT(RES43602_PARLDO_PU); in si_pmu_switch_on_PARLDO()
4894 W_REG(osh, &pmu->max_res_mask, mask); in si_pmu_switch_on_PARLDO()
4920 switch (CHIPID(sih->chip)) { in si_pmu_switch_off_PARLDO()
4923 mask = R_REG(osh, &pmu->min_res_mask) & ~PMURES_BIT(RES43602_PARLDO_PU); in si_pmu_switch_off_PARLDO()
4924 W_REG(osh, &pmu->min_res_mask, mask); in si_pmu_switch_off_PARLDO()
4925 mask = R_REG(osh, &pmu->max_res_mask) & ~PMURES_BIT(RES43602_PARLDO_PU); in si_pmu_switch_off_PARLDO()
4926 W_REG(osh, &pmu->max_res_mask, mask); in si_pmu_switch_off_PARLDO()
4948 if ((CHIPID(sih->chip) == BCM4360_CHIP_ID) || in BCMATTACHFN()
4949 (CHIPID(sih->chip) == BCM43460_CHIP_ID) || in BCMATTACHFN()
4950 (CHIPID(sih->chip) == BCM43526_CHIP_ID) || in BCMATTACHFN()
4951 (CHIPID(sih->chip) == BCM4352_CHIP_ID) || in BCMATTACHFN()
4952 BCM43602_CHIP(sih->chip)) { in BCMATTACHFN()
4997 * given x-tal frequency, returns BaseBand vcofreq with fraction in 100Hz
5007 p1div; /* predivider: divides x-tal freq */ in si_pmu_get_bb_vcofreq()
5013 if ((CHIPID(sih->chip) == BCM4360_CHIP_ID) || in si_pmu_get_bb_vcofreq()
5014 (CHIPID(sih->chip) == BCM43460_CHIP_ID) || in si_pmu_get_bb_vcofreq()
5015 (CHIPID(sih->chip) == BCM43526_CHIP_ID) || in si_pmu_get_bb_vcofreq()
5016 (CHIPID(sih->chip) == BCM4352_CHIP_ID) || in si_pmu_get_bb_vcofreq()
5017 BCM43602_CHIP(sih->chip)) { in si_pmu_get_bb_vcofreq()
5021 p1div = 1; /* do not divide x-tal frequency */ in si_pmu_get_bb_vcofreq()
5025 } else if ((BCM4369_CHIP(sih->chip) && in si_pmu_get_bb_vcofreq()
5026 CST4369_CHIPMODE_PCIE(sih->chipst)) || in si_pmu_get_bb_vcofreq()
5027 BCM4376_CHIP(sih->chip) || in si_pmu_get_bb_vcofreq()
5028 BCM4378_CHIP(sih->chip) || in si_pmu_get_bb_vcofreq()
5029 (BCM4362_CHIP(sih->chip) && in si_pmu_get_bb_vcofreq()
5030 CST4362_CHIPMODE_PCIE(sih->chipst))) { in si_pmu_get_bb_vcofreq()
5058 if ((int)xtal1 > (int)((0xffffffff - vcofrac) / ndiv_int)) { in si_pmu_get_bb_vcofreq()
5075 if (PMUREV(sih->pmurev) < 24) { in si_pmu_enb_slow_clk()
5076 PMU_ERROR(("si_pmu_enb_slow_clk: Not supported %d\n", PMUREV(sih->pmurev))); in si_pmu_enb_slow_clk()
5090 if (PMUREV(sih->pmurev) >= 38) { in si_pmu_enb_slow_clk()
5094 val = R_REG(osh, &pmu->slowclkperiod) | PMU30_ALPCLK_ONEMHZ_ENAB; in si_pmu_enb_slow_clk()
5096 if (PMUREV(sih->pmurev) >= 30) { in si_pmu_enb_slow_clk()
5106 * -usec wide toggle signal will be generated in si_pmu_enb_slow_clk()
5124 W_REG(osh, &pmu->slowclkperiod, val); in si_pmu_enb_slow_clk()
5131 * Initializes PLL given an x-tal frequency.
5135 * xtalfreq : x-tal frequency in [KHz]
5148 ASSERT(sih->cccaps & CC_CAP_PMU); in BCMATTACHFN()
5159 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
5163 if (CHIPREV(sih->chiprev) > 2) in BCMATTACHFN()
5186 CHIPID(sih->chip), chn, 8), CHIPREV(sih->chiprev), PMUREV(sih->pmurev))); in BCMATTACHFN()
5211 ASSERT(sih->cccaps & CC_CAP_PMU); in BCMPOSTTRAPFN()
5222 switch (CHIPID(sih->chip)) { in BCMPOSTTRAPFN()
5227 if (sih->chipst & CST4360_XTAL_40MZ) in BCMPOSTTRAPFN()
5263 CHIPID(sih->chip), chn, 8), CHIPREV(sih->chiprev), in BCMPOSTTRAPFN()
5264 PMUREV(sih->pmurev), clock)); in BCMPOSTTRAPFN()
5294 W_REG(osh, &pmu->pllcontrol_addr, pll0 + PMU5_PLL_P1P2_OFF); in BCMPOSTTRAPFN()
5295 (void)R_REG(osh, &pmu->pllcontrol_addr); in BCMPOSTTRAPFN()
5296 tmp = R_REG(osh, &pmu->pllcontrol_data); in BCMPOSTTRAPFN()
5300 W_REG(osh, &pmu->pllcontrol_addr, pll0 + PMU5_PLL_M14_OFF); in BCMPOSTTRAPFN()
5301 (void)R_REG(osh, &pmu->pllcontrol_addr); in BCMPOSTTRAPFN()
5302 tmp = R_REG(osh, &pmu->pllcontrol_data); in BCMPOSTTRAPFN()
5303 div = (tmp >> ((m - 1) * PMU5_PLL_MDIV_WIDTH)) & PMU5_PLL_MDIV_MASK; in BCMPOSTTRAPFN()
5305 W_REG(osh, &pmu->pllcontrol_addr, pll0 + PMU5_PLL_NM5_OFF); in BCMPOSTTRAPFN()
5306 (void)R_REG(osh, &pmu->pllcontrol_addr); in BCMPOSTTRAPFN()
5307 tmp = R_REG(osh, &pmu->pllcontrol_data); in BCMPOSTTRAPFN()
5335 ASSERT(sih->cccaps & CC_CAP_PMU); in BCMPOSTTRAPFN()
5346 switch (CHIPID(sih->chip)) { in BCMPOSTTRAPFN()
5386 CHIPID(sih->chip), chn, 8), CHIPREV(sih->chiprev), in BCMPOSTTRAPFN()
5387 PMUREV(sih->pmurev), clock)); in BCMPOSTTRAPFN()
5408 ASSERT(sih->cccaps & CC_CAP_PMU); in BCMPOSTTRAPFN()
5419 if (BCM4369_CHIP(sih->chip) || in BCMPOSTTRAPFN()
5420 BCM4376_CHIP(sih->chip) || in BCMPOSTTRAPFN()
5421 BCM4378_CHIP(sih->chip) || in BCMPOSTTRAPFN()
5422 BCM4385_CHIP(sih->chip) || in BCMPOSTTRAPFN()
5423 BCM4387_CHIP(sih->chip) || in BCMPOSTTRAPFN()
5424 BCM4388_CHIP(sih->chip) || in BCMPOSTTRAPFN()
5425 BCM4389_CHIP(sih->chip) || in BCMPOSTTRAPFN()
5426 BCM4397_CHIP(sih->chip) || in BCMPOSTTRAPFN()
5427 BCM4362_CHIP(sih->chip)) { in BCMPOSTTRAPFN()
5429 } else if ((PMUREV(sih->pmurev) >= 5) && in BCMPOSTTRAPFN()
5430 !((CHIPID(sih->chip) == BCM4360_CHIP_ID) || in BCMPOSTTRAPFN()
5431 (CHIPID(sih->chip) == BCM4352_CHIP_ID) || in BCMPOSTTRAPFN()
5432 (CHIPID(sih->chip) == BCM43526_CHIP_ID) || in BCMPOSTTRAPFN()
5433 (CHIPID(sih->chip) == BCM43460_CHIP_ID) || in BCMPOSTTRAPFN()
5434 (CHIPID(sih->chip) == BCM43012_CHIP_ID) || in BCMPOSTTRAPFN()
5435 (CHIPID(sih->chip) == BCM43013_CHIP_ID) || in BCMPOSTTRAPFN()
5436 (CHIPID(sih->chip) == BCM43014_CHIP_ID) || in BCMPOSTTRAPFN()
5440 if (BCM43602_CHIP(sih->chip)) { in BCMPOSTTRAPFN()
5449 if ((CHIPID(sih->chip) == BCM43012_CHIP_ID) || in BCMPOSTTRAPFN()
5450 (CHIPID(sih->chip) == BCM43013_CHIP_ID) || in BCMPOSTTRAPFN()
5451 (CHIPID(sih->chip) == BCM43014_CHIP_ID)) { in BCMPOSTTRAPFN()
5519 ASSERT(sih->cccaps & CC_CAP_PMU); in BCMINITFN()
5530 if ((PMUREV(sih->pmurev) >= 5) && in BCMINITFN()
5531 !((BCM4369_CHIP(sih->chip)) || in BCMINITFN()
5532 (BCM4362_CHIP(sih->chip)) || in BCMINITFN()
5533 BCM43602_CHIP(sih->chip) || in BCMINITFN()
5534 (CHIPID(sih->chip) == BCM43012_CHIP_ID) || in BCMINITFN()
5535 (CHIPID(sih->chip) == BCM43013_CHIP_ID) || in BCMINITFN()
5536 (CHIPID(sih->chip) == BCM43014_CHIP_ID) || in BCMINITFN()
5537 BCM4376_CHIP(sih->chip) || in BCMINITFN()
5538 BCM4378_CHIP(sih->chip) || in BCMINITFN()
5539 BCM4387_CHIP(sih->chip) || in BCMINITFN()
5540 BCM4388_CHIP(sih->chip) || in BCMINITFN()
5541 BCM4389_CHIP(sih->chip) || in BCMINITFN()
5542 BCM4397_CHIP(sih->chip) || in BCMINITFN()
5602 start = R_REG(osh, &pmu->pmutimer); in BCMINITFN()
5604 if (start != R_REG(osh, &pmu->pmutimer)) in BCMINITFN()
5605 start = R_REG(osh, &pmu->pmutimer); in BCMINITFN()
5607 end = R_REG(osh, &pmu->pmutimer); in BCMINITFN()
5608 if (end != R_REG(osh, &pmu->pmutimer)) in BCMINITFN()
5609 end = R_REG(osh, &pmu->pmutimer); in BCMINITFN()
5610 delta = end - start; in BCMINITFN()
5663 * 'drivestrength': desired pad drive strength in mA. Drive strength of 0 requests tri-state (if
5675 * but the bit definitions are chip-specific. We are keeping this function available in BCMINITFN()
5691 ASSERT(sih->cccaps & CC_CAP_PMU); in BCMATTACHFN()
5708 if (PMUREV(sih->pmurev) == 1) in BCMATTACHFN()
5709 AND_REG(osh, &pmu->pmucontrol, ~PCTL_NOILP_ON_WAIT); in BCMATTACHFN()
5710 else if (PMUREV(sih->pmurev) >= 2) in BCMATTACHFN()
5711 OR_REG(osh, &pmu->pmucontrol, PCTL_NOILP_ON_WAIT); in BCMATTACHFN()
5714 if ((PMUREV(sih->pmurev) >= 26) && (PMUREV(sih->pmurev) != 27)) { in BCMATTACHFN()
5748 rsc_num = rsc->macphy_clkavail; in si_pmu_rsrc_macphy_clk_deps()
5750 rsc_num = rsc->macphy_aux_clkavail; in si_pmu_rsrc_macphy_clk_deps()
5752 rsc_num = rsc->macphy_scan_clkavail; in si_pmu_rsrc_macphy_clk_deps()
5783 rsrc = (PMURES_BIT(rsc->macphy_scan_clkavail) | in si_pmu_set_mac_rsrc_req_sc()
5784 PMURES_BIT(rsc->dig_ready)); in si_pmu_set_mac_rsrc_req_sc()
5789 W_REG(osh, &pmu->mac_res_req_timer2, PMU32_MAC_SCAN_RSRC_REQ_TIMER); in si_pmu_set_mac_rsrc_req_sc()
5790 W_REG(osh, &pmu->mac_res_req_mask2, deps); in si_pmu_set_mac_rsrc_req_sc()
5815 deps = si_pmu_res_deps(sih, osh, pmu, PMURES_BIT(rsc->ht_avail), FALSE); in BCMATTACHFN()
5816 deps |= PMURES_BIT(rsc->ht_avail); in BCMATTACHFN()
5843 if (rsc->cb_ready == NO_SUCH_RESOURCE) { in BCMATTACHFN()
5846 deps = si_pmu_res_deps(sih, osh, pmu, PMURES_BIT(rsc->cb_ready), FALSE); in BCMATTACHFN()
5847 deps |= PMURES_BIT(rsc->cb_ready); in BCMATTACHFN()
5873 W_REG(osh, &pmu->mac_res_req_timer, PMU32_MAC_MAIN_RSRC_REQ_TIMER); in si_pmu_set_mac_rsrc_req()
5874 W_REG(osh, &pmu->mac_res_req_mask, si_pmu_rsrc_macphy_clk_deps(sih, osh, macunit)); in si_pmu_set_mac_rsrc_req()
5876 W_REG(osh, &pmu->mac_res_req_timer1, PMU32_MAC_AUX_RSRC_REQ_TIMER); in si_pmu_set_mac_rsrc_req()
5877 W_REG(osh, &pmu->mac_res_req_mask1, si_pmu_rsrc_macphy_clk_deps(sih, osh, macunit)); in si_pmu_set_mac_rsrc_req()
5879 W_REG(osh, &pmu->mac_res_req_timer2, PMU32_MAC_SCAN_RSRC_REQ_TIMER); in si_pmu_set_mac_rsrc_req()
5880 W_REG(osh, &pmu->mac_res_req_mask2, si_pmu_rsrc_macphy_clk_deps(sih, osh, macunit)); in si_pmu_set_mac_rsrc_req()
5907 W_REG(osh, &pmu->res_table_sel, rsrc); in BCMINITFN()
5908 if (PMUREV(sih->pmurev) >= 30) in BCMINITFN()
5909 uptime = (R_REG(osh, &pmu->res_updn_timer) >> 16) & 0x7fff; in BCMINITFN()
5910 else if (PMUREV(sih->pmurev) >= 13) in BCMINITFN()
5911 uptime = (R_REG(osh, &pmu->res_updn_timer) >> 16) & 0x3ff; in BCMINITFN()
5913 uptime = (R_REG(osh, &pmu->res_updn_timer) >> 8) & 0xff; in BCMINITFN()
5926 min_mask = R_REG(osh, &pmu->min_res_mask); in BCMINITFN()
5959 W_REG(osh, &pmu->res_table_sel, i); in si_pmu_res_deps()
5960 deps |= R_REG(osh, &pmu->res_dep_mask); in si_pmu_res_deps()
6006 ASSERT(sih->cccaps & CC_CAP_PMU); in si_pmu_otp_power()
6027 * Please refer to http://hwnbu-twiki.broadcom.com/bin/view/Mwgroup/ChipcommonRev45 in si_pmu_otp_power()
6029 if (CCREV(sih->ccrev) == 45) { in si_pmu_otp_power()
6042 switch (CHIPID(sih->chip)) { in si_pmu_otp_power()
6057 rsrcs = PMURES_BIT(rsc->otp_pu); in si_pmu_otp_power()
6080 min_mask = R_REG(osh, &pmu->min_res_mask); in si_pmu_otp_power()
6088 W_REG(osh, &pmu->min_res_mask, min_mask); in si_pmu_otp_power()
6091 SPINWAIT(!(R_REG(osh, &pmu->res_state) & rsrcs), in si_pmu_otp_power()
6093 ASSERT(R_REG(osh, &pmu->res_state) & rsrcs); in si_pmu_otp_power()
6102 min_mask = R_REG(osh, &pmu->min_res_mask); in si_pmu_otp_power()
6113 W_REG(osh, &pmu->min_res_mask, min_mask); in si_pmu_otp_power()
6124 * affect other chips. Once the correct spin-wait value is updated by the in si_pmu_otp_power()
6176 /* PLL CTRL registers are meaningless under QT, return the pre-configured freq */ in si_pmu_pll28nm_fvco()
6217 switch (CHIPID(sih->chip)) { in si_pmu_is_otp_powered()
6230 st = (R_REG(osh, &pmu->res_state) & PMURES_BIT(rsc->otp_pu)) != 0; in si_pmu_is_otp_powered()
6259 uint32 ext_lpo_isclock; /* On e.g. 43602a0, either x-tal or clock can be on LPO pins */ in BCMATTACHFN()
6282 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
6295 ext_lpo_avail = R_REG(osh, &pmu->pmustatus) & EXT_LPO_AVAIL; in BCMATTACHFN()
6298 ext_lpo_avail = R_REG(osh, &pmu->pmustatus) & EXT_LPO_AVAIL; in BCMATTACHFN()
6309 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
6321 lpo_sel = R_REG(osh, &pmu->pmucontrol) & LPO_SEL; in BCMATTACHFN()
6324 lpo_sel = R_REG(osh, &pmu->pmucontrol) & LPO_SEL; in BCMATTACHFN()
6332 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
6343 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
6354 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
6371 lpo_sel = R_REG(osh, &pmu->pmucontrol) & LPO_SEL; in BCMATTACHFN()
6375 lpo_sel = R_REG(osh, &pmu->pmucontrol) & LPO_SEL; in BCMATTACHFN()
6389 if ((PMUREV(sih->pmurev) >= 33)) { in BCMATTACHFN()
6403 switch (CHIPID(sih->chip)) { in si_pmu_fast_lpo_locked()
6436 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
6473 if ((LHLREV(sih->lhlrev) >= 6) && !PMU_FLL_PU_ENAB()) { in BCMATTACHFN()
6511 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
6547 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
6609 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
6645 if (BCM4369_CHIP(sih->chip) && (CHIPREV(sih->chiprev) == 0)) { in BCMATTACHFN()
6658 * cbuck rsrc 0 - PWM and abuck rsrc 0 - Auto, rsrc 1 - PWM in BCMATTACHFN()
6669 /* asr voltage adjust PWM - 0.8V */ in BCMATTACHFN()
6689 /* Enable MISCLDO only for A0, MEMLPLDO_adj -0.7V, Disable LPLDO power up */ in BCMATTACHFN()
6693 if (!(BCM4389_CHIP(sih->chip) || BCM4388_CHIP(sih->chip) || BCM4397_CHIP(sih->chip) || in BCMATTACHFN()
6694 BCM4387_CHIP(sih->chip))) { in BCMATTACHFN()
6696 ((CHIPREV(sih->chiprev) == 0) ? 1 : 0) << in BCMATTACHFN()
6792 * cbuck rsrc 0 - PWM and abuck rsrc 0 - Auto, rsrc 1 - PWM in BCMATTACHFN()
6797 /* asr voltage adjust PWM - 0.8V */ in BCMATTACHFN()
6824 if (PMUREV(sih->pmurev) < 39) { in BCMATTACHFN()
6911 /* H/W JIRA http://jira.broadcom.com/browse/HW4387-825 in BCMATTACHFN()
6914 if (PMUREV(sih->pmurev) == 38) { in BCMATTACHFN()
6920 /* WAR for jira HW4387-922 */ in BCMATTACHFN()
6968 /* Disable lq_clk - HW4387-254 */ in BCMATTACHFN()
7003 /* SW WAR for 4389B0(rev 01) issue - HW4387-922. 4389C0(rev 02) already has HW fix */ in BCMATTACHFN()
7004 if (CHIPREV(sih->chiprev) == 1) { in BCMATTACHFN()
7019 * cbuck rsrc 0 - PWM and abuck rsrc 0 - Auto, rsrc 1 - PWM in BCMATTACHFN()
7026 /* asr voltage adjust PWM - 0.8V */ in BCMATTACHFN()
7046 /* Enable MISCLDO, MEMLPLDO_adj -0.7V, Disable LPLDO power up */ in BCMATTACHFN()
7114 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
7117 val = R_REG(osh, &pmu->max_res_mask); in BCMATTACHFN()
7118 W_REG(osh, &pmu->fis_start_min_res_mask, val); in BCMATTACHFN()
7120 val = R_REG(osh, &pmu->min_res_mask); in BCMATTACHFN()
7121 W_REG(osh, &pmu->fis_min_res_mask, val); in BCMATTACHFN()
7123 W_REG(osh, &pmu->fis_ctrl_status, in BCMATTACHFN()
7128 val = R_REG(osh, &pmu->max_res_mask); in BCMATTACHFN()
7129 W_REG(osh, &pmu->fis_start_min_res_mask, val); in BCMATTACHFN()
7131 val = R_REG(osh, &pmu->min_res_mask); in BCMATTACHFN()
7132 W_REG(osh, &pmu->fis_min_res_mask, val); in BCMATTACHFN()
7134 W_REG(osh, &pmu->fis_ctrl_status, in BCMATTACHFN()
7139 val = R_REG(osh, &pmu->max_res_mask); in BCMATTACHFN()
7140 W_REG(osh, &pmu->fis_start_min_res_mask, val); in BCMATTACHFN()
7142 val = R_REG(osh, &pmu->min_res_mask); in BCMATTACHFN()
7143 W_REG(osh, &pmu->fis_min_res_mask, val); in BCMATTACHFN()
7145 W_REG(osh, &pmu->fis_ctrl_status, in BCMATTACHFN()
7165 if (PMUREV(sih->pmurev) >= 36) { in BCMATTACHFN()
7193 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
7216 W_REG(osh, &pmu->rsrc_event0, PMURES_BIT(rsrc_slp)); in BCMATTACHFN()
7228 ASSERT(sih->cccaps & CC_CAP_PMU); in BCMATTACHFN()
7248 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
7268 if (sih->lpflags & LPFLAGS_SI_FORCE_PWM_WHEN_RADIO_ON) { in BCMATTACHFN()
7313 /* Enable PMU sleep mode0 (DS0-PS0) */ in BCMATTACHFN()
7331 * Stretch the ALP and HT clocks after de-asserting in BCMATTACHFN()
7333 * DP FIFO, in certain cases the clock is getting de-asserted in BCMATTACHFN()
7336 W_REG(osh, &pmu->clkstretch, 0x0fff0fff); in BCMATTACHFN()
7343 if (R_REG(osh, &pmu->pmustatus) & PST_EXTLPOAVAIL) { in BCMATTACHFN()
7380 if ((PMUREV(sih->pmurev) >= 33) && FASTLPO_ENAB()) { in BCMATTACHFN()
7400 * Stretch the ALP and HT clocks after de-asserting in BCMATTACHFN()
7402 * DP FIFO, in certain cases the clock is getting de-asserted in BCMATTACHFN()
7406 W_REG(osh, &pmu->clkstretch, 0x0fff0fff); in BCMATTACHFN()
7414 if (R_REG(osh, &pmu->pmustatus) & PST_EXTLPOAVAIL) { in BCMATTACHFN()
7439 if (CHIPREV(sih->chiprev) == 0) { in BCMATTACHFN()
7452 if (CHIPID(sih->chip) != BCM4377_CHIP_ID) { in BCMATTACHFN()
7456 if ((PMUREV(sih->pmurev) >= 33) && FASTLPO_ENAB()) { in BCMATTACHFN()
7486 if (R_REG(osh, &pmu->pmustatus) & PST_EXTLPOAVAIL) { in BCMATTACHFN()
7494 /* JIRA: SWWLAN-228979 in BCMATTACHFN()
7548 if (CHIPID(sih->chip) == BCM4378_CHIP_GRPID) { in BCMATTACHFN()
7594 min_mask = R_REG(osh, &pmu->min_res_mask) | in BCMATTACHFN()
7597 W_REG(osh, &pmu->min_res_mask, min_mask); in BCMATTACHFN()
7611 if (R_REG(osh, &pmu->pmustatus) & PST_EXTLPOAVAIL) { in BCMATTACHFN()
7700 /* Set up HW based switch-off of select BBPLL channels when SCAN-only mode in BCMATTACHFN()
7724 if (CHIPID(sih->chip) == BCM4397_CHIP_GRPID) { in BCMATTACHFN()
7737 if (CHIPID(sih->chip) == BCM4397_CHIP_GRPID) { in BCMATTACHFN()
7745 if (sih->chip != BCM4397_CHIP_ID) { in BCMATTACHFN()
7769 W_REG(osh, &pmu->extwakereqmask[0], deps); in BCMATTACHFN()
7789 min_mask = R_REG(osh, &pmu->min_res_mask) | in BCMATTACHFN()
7792 W_REG(osh, &pmu->min_res_mask, min_mask); in BCMATTACHFN()
7809 if (R_REG(osh, &pmu->pmustatus) & PST_EXTLPOAVAIL) { in BCMATTACHFN()
7883 /* Set up HW based switch-off of select BBPLL channels when SCAN-only mode in BCMATTACHFN()
7913 if (CHIPID(sih->chip) == BCM4397_CHIP_GRPID) { in BCMATTACHFN()
7921 if (sih->chip != BCM4397_CHIP_ID) { in BCMATTACHFN()
7941 if (PMUREV(sih->pmurev) == 39) { in BCMATTACHFN()
7959 switch (CHIPID(sih->chip)) { in si_pmu_openloop_cal()
7976 int32 a1 = -27, a2 = -15, b1 = 18704, b2 = 7531, a3, y1, y2, b3, y3; in si_pmu_openloop_cal_43012()
7997 currtemp = (currtemp == 0)?-1: currtemp; in si_pmu_openloop_cal_43012()
8019 OR_REG(osh, &pmu->pmucontrol, PCTL_PLL_PLLCTL_UPD); in si_pmu_openloop_cal_43012()
8030 OR_REG(osh, &pmu->pmucontrol, PCTL_PLL_PLLCTL_UPD); in si_pmu_openloop_cal_43012()
8034 OR_REG(osh, &pmu->pmucontrol, PCTL_PLL_PLLCTL_UPD); in si_pmu_openloop_cal_43012()
8047 b3 = b1 + (((b2-b1)/(y2 - y1)) * (dco_code - y1)); in si_pmu_openloop_cal_43012()
8049 a3 = (b3 - dco_code) / currtemp; in si_pmu_openloop_cal_43012()
8050 y3 = b3 - (a3 * 125); in si_pmu_openloop_cal_43012()
8053 a3 = (dco_code - b3) / currtemp; in si_pmu_openloop_cal_43012()
8069 OR_REG(osh, &pmu->pmucontrol, PCTL_PLL_PLLCTL_UPD); in si_pmu_openloop_cal_43012()
8093 OR_REG(osh, &pmu->pmucontrol, PCTL_PLL_PLLCTL_UPD); in si_pmu_openloop_cal_43012()
8095 /* 230-220MHz). Update SAVE_RESTORE up/down times accordingly */ in si_pmu_openloop_cal_43012()
8096 W_REG(osh, &pmu->res_table_sel, RES43012_SR_SAVE_RESTORE); in si_pmu_openloop_cal_43012()
8097 W_REG(osh, &pmu->res_updn_timer, 0x01800180); in si_pmu_openloop_cal_43012()
8129 switch (CHIPID(sih->chip)) { in si_pmu_slow_clk_reinit()
8149 ASSERT(sih->cccaps & CC_CAP_PMU); in BCMATTACHFN()
8151 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
8183 ASSERT(sih->cccaps & CC_CAP_PMU); in si_pmu_waitforclk_on_backplane()
8194 SPINWAIT(((R_REG(osh, &pmu->pmustatus) & clk) != clk), delay_val); in si_pmu_waitforclk_on_backplane()
8195 val = R_REG(osh, &pmu->pmustatus) & clk; in si_pmu_waitforclk_on_backplane()
8216 if (PMUREV(sih->pmurev) < 10) in BCMATTACHFN()
8219 ASSERT(sih->cccaps & CC_CAP_PMU); in BCMATTACHFN()
8230 if ((CHIPID(sih->chip) == BCM43012_CHIP_ID) || in BCMATTACHFN()
8231 (CHIPID(sih->chip) == BCM43013_CHIP_ID) || in BCMATTACHFN()
8232 (CHIPID(sih->chip) == BCM43014_CHIP_ID) || in BCMATTACHFN()
8233 (PMUREV(sih->pmurev) >= 22)) in BCMATTACHFN()
8234 pmustat_lpo = !(R_REG(osh, &pmu->pmucontrol) & PCTL_LPO_SEL); in BCMATTACHFN()
8236 pmustat_lpo = R_REG(osh, &pmu->pmustatus) & PST_EXTLPOAVAIL; in BCMATTACHFN()
8242 W_REG(osh, &pmu->pmu_xtalfreq, 1U << PMU_XTALFREQ_REG_MEASURE_SHIFT); in BCMATTACHFN()
8248 ilp_ctr = R_REG(osh, &pmu->pmu_xtalfreq) & PMU_XTALFREQ_REG_ILPCTR_MASK; in BCMATTACHFN()
8251 W_REG(osh, &pmu->pmu_xtalfreq, 0); in BCMATTACHFN()
8267 /** Update min/max resources after SR-ASM download to d11 txfifo */
8287 switch (CHIPID(sih->chip)) { in si_pmu_res_minmax_update()
8314 W_REG(osh, &pmu->min_res_mask, min_mask); in si_pmu_res_minmax_update()
8318 W_REG(osh, &pmu->max_res_mask, max_mask); in si_pmu_res_minmax_update()
8377 * It is good to avoid re-reading PMU registers as: 1. reading regs is slow
8400 if (PMUREV(sih->pmurev) < 5) in BCMATTACHFN()
8404 cnt = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT; in BCMATTACHFN()
8409 cnt = (sih->pmucaps & PCAP5_PC_MASK) >> PCAP5_PC_SHIFT; in BCMATTACHFN()
8415 cnt = (sih->pmucaps & PCAP5_VC_MASK) >> PCAP5_VC_SHIFT; in BCMATTACHFN()
8421 cnt = (sih->pmucaps & PCAP5_CC_MASK) >> PCAP5_CC_SHIFT; in BCMATTACHFN()
8436 if ((PMUREV(sih->pmurev) > 27) && ARRAYSIZE(pmuregsdump) != 0) { in BCMATTACHFN()
8478 if (PMUREV(sih->pmurev) < 5) in BCMPOSTTRAPFN()
8493 cnt = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT; in BCMPOSTTRAPFN()
8497 W_REG(osh, &pmu->res_table_sel, i); in BCMPOSTTRAPFN()
8498 *p32++ = R_REG(osh, &pmu->res_dep_mask); in BCMPOSTTRAPFN()
8499 *p32++ = R_REG(osh, &pmu->res_updn_timer); in BCMPOSTTRAPFN()
8503 cnt = (sih->pmucaps & PCAP5_PC_MASK) >> PCAP5_PC_SHIFT; in BCMPOSTTRAPFN()
8511 cnt = (sih->pmucaps & PCAP5_VC_MASK) >> PCAP5_VC_SHIFT; in BCMPOSTTRAPFN()
8518 cnt = (sih->pmucaps & PCAP5_CC_MASK) >> PCAP5_CC_SHIFT; in BCMPOSTTRAPFN()
8535 if ((PMUREV(sih->pmurev) > 27)) { in BCMPOSTTRAPFN()
8576 /* Mark the location where these registers are dumped to avoid a re-read in in BCMPOSTTRAPFN()
8579 rodata_pmuregdump_ptr = (p32 - (2 * pmu_totalsize)); in BCMPOSTTRAPFN()
8620 OR_REG(osh, &pmu->min_res_mask, min_mask); in si_pmu_min_res_set()
8623 AND_REG(osh, &pmu->min_res_mask, ~min_mask); in si_pmu_min_res_set()
8659 switch (CHIPID(sih->chip)) { in si_pmu_soft_start_params()
8678 if (BCM4378_CHIP(sih->chip) && PMUREV(sih->pmurev) == 37) { in si_pmu_soft_start_params()
8723 *res = -1; in si_pmu_ldo3p3_soft_start_get()
8792 switch (CHIPID(sih->chip)) { in si_pmu_min_res_ldo3p3_set()
8833 min_mask = PMURES_BIT(rsc->otp_pu); in si_pmu_min_res_otp_pu_set()
8847 switch (CHIPID(sih->chip)) { in BCMPOSTTRAPFN()
8884 W_REG(hnd_osh, &pmu->pmuintstatus, in hnd_pmu_clr_int_sts_req_active()
8886 (void)R_REG(hnd_osh, &pmu->pmuintstatus); in hnd_pmu_clr_int_sts_req_active()
8887 res_req_timer = R_REG(hnd_osh, &pmu->res_req_timer); in hnd_pmu_clr_int_sts_req_active()
8888 W_REG(hnd_osh, &pmu->res_req_timer, in hnd_pmu_clr_int_sts_req_active()
8890 (void)R_REG(hnd_osh, &pmu->res_req_timer); in hnd_pmu_clr_int_sts_req_active()
8909 W_REG(osh, &pmu->min_res_mask, min_res_mask); in si_pmu_set_min_res_mask()
8940 * 4389B0/C0 - WL and BT turn on WAR,
8942 * - global bit[195] / bit[3] - enable legacy pmu_wakeup to make
8944 * - global bit[206] / bit[14] - perst_wake_en
8949 if (PMUREV(sih->pmurev) == 40) { in si_pmu_dmn1_perst_wakeup()
8968 * TRUE - Programs the PLLCTRL6 with xtal and returns value written in pllctrl6 register.
8969 * FALSE - returns 0 if xtal programming is same as pllctrl6 register else retruns value of
8985 r = ((armclk * 10 * PMU4369_PLL6VAL_P1DIV * PMU4369_PLL6VAL_PRE_SCALE) / xtal_scale) - in si_pmu_pll6val_armclk_calc()
8996 W_REG(osh, &pmu->pllcontrol_addr, PMU1_PLL0_PLLCTL6); in si_pmu_pll6val_armclk_calc()
8997 W_REG(osh, &pmu->pllcontrol_data, pll6val); in si_pmu_pll6val_armclk_calc()
8999 W_REG(osh, &pmu->pllcontrol_addr, PMU1_PLL0_PLLCTL6); in si_pmu_pll6val_armclk_calc()
9000 if (pll6val == R_REG(osh, &pmu->pllcontrol_data)) in si_pmu_pll6val_armclk_calc()
9182 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
9204 switch (CHIPID(sih->chip)) { in BCMATTACHFN()
9226 * //core-n active duration : pmu_rsrc_state(CORE_RDY_AUX)
9228 * //core-n active duration : pmu_rsrc_state(CORE_RDY_AUX)
9236 //deep-sleep duration : pmu_rsrc_state(XTAL_PU)
9238 //deep-sleep entry count : pmu_rsrc_state(XTAL_PU)
9240 //core-n active duration : pmu_rsrc_state(CORE_RDY_MAIN)
9242 //core-n active duration : pmu_rsrc_state(CORE_RDY_MAIN)
9251 W_REG(osh, &pmu->pmu_statstimer_addr, timerid); in si_pmustatstimer_update()
9259 W_REG(osh, &pmu->pmu_statstimer_ctrl, stats_timer_ctrl); in si_pmustatstimer_update()
9260 W_REG(osh, &pmu->pmu_statstimer_N, 0); in si_pmustatstimer_update()
9279 OR_REG(osh, &pmu->pmuintmask0, PMU_INT_STAT_TIMER_INT_MASK); in si_pmustatstimer_int_enable()
9301 AND_REG(osh, &pmu->pmuintmask0, ~PMU_INT_STAT_TIMER_INT_MASK); in si_pmustatstimer_int_disable()
9326 core_cap_ext = R_REG(osh, &pmu->core_cap_ext); in si_pmustatstimer_init()
9334 OR_REG(osh, &pmu->pmuintmask0, PMU_INT_STAT_TIMER_INT_MASK); in si_pmustatstimer_init()
9361 pmucapabilities = R_REG(osh, &pmu->pmucapabilities); in si_pmustatstimer_dump()
9362 core_cap_ext = R_REG(osh, &pmu->core_cap_ext); in si_pmustatstimer_dump()
9363 AlpPeriod = R_REG(osh, &pmu->slowclkperiod); in si_pmustatstimer_dump()
9364 ILPPeriod = R_REG(osh, &pmu->ILPPeriod); in si_pmustatstimer_dump()
9371 pmuintstatus = R_REG(osh, &pmu->pmuintstatus); in si_pmustatstimer_dump()
9372 pmuintmask0 = R_REG(osh, &pmu->pmuintmask0); in si_pmustatstimer_dump()
9381 pmuintmask0, pmuintstatus, PMUREV(sih->pmurev))); in si_pmustatstimer_dump()
9384 W_REG(osh, &pmu->pmu_statstimer_addr, i); in si_pmustatstimer_dump()
9385 stat_timer_ctrl = R_REG(osh, &pmu->pmu_statstimer_ctrl); in si_pmustatstimer_dump()
9386 stat_timer_N = R_REG(osh, &pmu->pmu_statstimer_N); in si_pmustatstimer_dump()
9413 W_REG(osh, &pmu->pmu_statstimer_addr, timerid); in si_pmustatstimer_start()
9414 OR_REG(osh, &pmu->pmu_statstimer_ctrl, PMU_ST_ENAB << PMU_ST_EN_SHIFT); in si_pmustatstimer_start()
9438 W_REG(osh, &pmu->pmu_statstimer_addr, timerid); in si_pmustatstimer_stop()
9439 AND_REG(osh, &pmu->pmu_statstimer_ctrl, ~(PMU_ST_ENAB << PMU_ST_EN_SHIFT)); in si_pmustatstimer_stop()
9461 W_REG(osh, &pmu->pmu_statstimer_addr, timerid); in si_pmustatstimer_clear()
9462 W_REG(osh, &pmu->pmu_statstimer_N, 0); in si_pmustatstimer_clear()
9488 core_cap_ext = R_REG(osh, &pmu->core_cap_ext); in si_pmustatstimer_clear_overflow()
9492 W_REG(osh, &pmu->pmu_statstimer_addr, i); in si_pmustatstimer_clear_overflow()
9493 timerN = R_REG(osh, &pmu->pmu_statstimer_N); in si_pmustatstimer_clear_overflow()
9495 PMU_ERROR(("pmustatstimer overflow clear - timerid : %d\n", i)); in si_pmustatstimer_clear_overflow()
9521 W_REG(osh, &pmu->pmu_statstimer_addr, timerid); in si_pmustatstimer_read()
9522 stats_timer_N = R_REG(osh, &pmu->pmu_statstimer_N); in si_pmustatstimer_read()
9580 * len parameter is dual purpose - On input it is length of the
9602 * Avoid re-read. If data is not there, then there could have been in BCMPOSTTRAPFN()
9643 if (PMUREV(sih->pmurev) >= 26) { in BCMPOSTTRAPFN()
9658 if (PMUREV(sih->pmurev) >= 26) { in BCMPOSTTRAPFN()
9680 switch (CHIPID(sih->chip)) { in si_pmu_mem_pwr_off()
9750 switch (CHIPID(sih->chip)) { in BCMPOSTTRAPFN()
9788 switch (CHIPID(sih->chip)) { in BCMPOSTTRAPFN()
9824 W_REG(osh, &pmu->pmuintmask0, 0); in BCMPOSTTRAPFN()
9826 pmu_intr_recvr_cnt = ((R_REG(osh, &pmu->core_cap_ext) & PCAP_EXT_PMU_INTR_RCVR_CNT_MASK) in BCMPOSTTRAPFN()
9830 W_REG(osh, &pmu->pmuintmask1, 0); in BCMPOSTTRAPFN()
9843 switch (CHIPID(sih->chip)) { in si_pmu_res_state_pwrsw_main_wait()
9889 if (PMUREV(sih->pmurev) == 40) { in si_pmu_reg_on_war_ext_wake_perst_set()
9891 * set PCIEPerstReq (bit-5) as a wake-up source in in si_pmu_reg_on_war_ext_wake_perst_set()
9894 W_REG(osh, &pmu->extwakemask0, PMU_EXT_WAKE_MASK_0_PCIE_PERST); in si_pmu_reg_on_war_ext_wake_perst_set()
9898 * be up during wake-up in ExtWakeReqMask0 (0x770) register in si_pmu_reg_on_war_ext_wake_perst_set()
9900 W_REG(osh, &pmu->extwakereqmask[0], REG_ON_WAR_PMU_EXT_WAKE_REQ_MASK0_VAL); in si_pmu_reg_on_war_ext_wake_perst_set()
9914 if (PMUREV(sih->pmurev) == 40) { in si_pmu_reg_on_war_ext_wake_perst_clear()
9916 val = R_REG(osh, &pmu->extwakeupstatus); in si_pmu_reg_on_war_ext_wake_perst_clear()
9917 W_REG(osh, &pmu->extwakeupstatus, val); in si_pmu_reg_on_war_ext_wake_perst_clear()